Samsung S3C2451X, Руководство пользователя

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Preliminary
USB2.0 DEVICE S3C2451X RISC MICROPROCESSOR
17-32
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MEMORY CURRENT ADDRESS REGISTER (MCAR)
Register Address R/W Description Reset Value
MCAR 0x4980_008C R Memory Current Address Register 0x0
MCAR# Bit R/W Description Initial State
MCAR [31:0] R This register should have memory current address to be
transferred using DMA Interface.
BURST FIFO CONTROL REGISTER(FCON)
Register Address R/W Description Reset Value
FCON 0x4980_0100 R/W Burst DMA transfer Control 0x0
MBAR# Bit R/W Description Initial State
Reserved [31:9] R/W Reserved 000000
DMAEN [8] R/W DMA enable 0
Rreserved [7:5] R/W Reserved 000
TF_CLR [4] R/W TX fifo clear 0
Reserved [3:1] R/W Reserved 000
RF_CLR [0] R/W RX fifo clear 0
BURST FIFO STATUS REGISTER(FSTAT)
Register Address R/W Description Reset Value
FSTAT 0x4980_0104 R/W Burst DMA transfer Status 0x0
FSTAT Bit R/W Description Initial State
Reserved [31:14] R Reserved
TF_FULL [13] R TX FIFO Full 0
TF_CNT [12:8] R # of data in TX fifo 0
Reserved [7:6] R Reserved 0
RF_FULL [5] R RX FIFO Full 0
RF_CNT [4:0] R # of data in RX fifo 0