Samsung S3C2451X, Руководство пользователя

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Preliminary
HSMMC CONTROLLER S3C2451X RISC MICROPROCESSOR
21-26
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
RESPONSE REGISTER
This register is used to store responses from SD cards.
Register Address R/W Description Reset Value
RSPREG0_0 0X4AC00010 ROC Response Register 0 (Channel 0) 0x0
RSPREG1_0 0X4AC00014 ROC Response Register 1 (Channel 0) 0x0
RSPREG2_0 0X4AC00018 ROC Response Register 2 (Channel 0) 0x0
RSPREG3_0 0X4AC0001C ROC Response Register 3 (Channel 0) 0x0
Register Address R/W Description Reset Value
RSPREG0_1 0X4A800010 ROC Response Register 0 (Channel 1) 0x0
RSPREG1_1 0X4A800014 ROC Response Register 1 (Channel 1) 0x0
RSPREG2_1 0X4A800018 ROC Response Register 2 (Channel 1) 0x0
RSPREG3_1 0X4A80001C ROC Response Register 3 (Channel 1) 0x0
Name Bit Description Initial
Value
CMDRS
P [127:0]
Command Response
The Table below describes the mapping of command responses from the SD
Bus to this register for each response type. In the table, R[] refers to a bit range
within the response data as transmitted on the SD Bus, REP[] refers to a bit
range within the
Response register.
128-bit Response bit order : {RSPREG3, RSPREG2, RSPREG1, RSPREG0}
Kind of Response Meaning of Response Response Field Response Register
R1, R1b (normal response) Card Status R [39:8] REP [31:0]
R1b (Auto CMD12 response) Card Status for Auto CMD12 R [39:8] REP [127:96]
R2 (CID, CSD register) CID or CSD reg. incl. R [127:8] REP [119:0]
R3 (OCR register) OCR register for memory R [39:8] REP [31:0]
R4 (OCR register) OCR register for I/O etc R [39:8] REP [31:0]
R5,R5b SDIO response R [39:8] REP [31:0]
R6 (Published RCA response) New published RCA[31:16] etc R [39:8] REP [31:0]
R7 ? R [39:8] REP [31:0]
Response Bit Definition for Each Response Type.
The Response Field indicates bit positions of “Responses” defined in the PHYSICAL LAYER SPECIFICATION
Version 1.01. The Table (upper) shows that most responses with a length of 48 (R[47:0]) have 32 bits of the
response data (R[39:8]) stored in the
Response register at REP[31:0]. Responses of type R1b (Auto CMD12
responses) have response data bits R[39:8] stored in the Response register at REP[127:96]. Responses with
length 136 (R[135:0]) have 120 bits of the response data (R[127:8]) stored in the Response register at
REP[119:0].
To be able to read the response status efficiently, the Host Controller only stores part of the response data in the
Response register. This enables the Host Driver to efficiently read 32 bits of response data in one read cycle on a