
UM10800
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© NXP Semiconductors N.V. 2016. All rights reserved.
User manual
Rev. 1.2 — 5 October 2016
17 of 487
NXP Semiconductors
UM10800
Chapter 4: LPC82x Nested Vectored Interrupt Controller (NVIC)
4.3.2 Non-Maskable Interrupt (NMI)
The part supports the NMI, which can be triggered by an peripheral interrupt or triggered
by software. The NMI has the highest priority exception other than the reset.
You can set up any peripheral interrupt listed in
as NMI using the NMISRC
register in the SYSCON block (
). To avoid using the same peripheral interrupt as
NMI exception and normal interrupt, disable the interrupt in the NVIC when you configure
it as NMI.
4.3.3 Vector table offset
The vector table contains the reset value of the stack pointer and the start addresses, also
called exception vectors, for all exception handlers. On system reset, the vector table is
located at address 0x0000 0000. Software can write to the VTOR register in the NVIC to
relocate the vector table start address to a different memory location. For a description of
the VTOR register, see the ARM Cortex-M0+ documentation (
26
PININT2_IRQ
Pin interrupt 2 or pattern
match engine slice 2
interrupt
PSTAT - pin interrupt status
27
PININT3_IRQ
Pin interrupt 3 or pattern
match engine slice 3
interrupt
PSTAT - pin interrupt status
28
PININT4_IRQ
Pin interrupt 4 or pattern
match engine slice 4
interrupt
PSTAT - pin interrupt status
29
PININT5_IRQ
Pin interrupt 5 or pattern
match engine slice 5
interrupt
PSTAT - pin interrupt status
30
PININT6_IRQ
Pin interrupt 6 or pattern
match engine slice 6
interrupt
PSTAT - pin interrupt status
31
PININT7_IRQ
Pin interrupt 7 or pattern
match engine slice 7
interrupt
PSTAT - pin interrupt status
Table 5.
Connection of interrupt sources to the NVIC
Interrupt
number
Name
Description
Flags