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EDR-5000
IM02602007E
Name
Description
Logic.LE2.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE2.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE3.Gate Out
Signal: Output of the logic gate
Logic.LE3.Timer Out
Signal: Timer Output
Logic.LE3.Out
Signal: Latched Output (Q)
Logic.LE3.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE3.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE3.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE3.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE4.Gate Out
Signal: Output of the logic gate
Logic.LE4.Timer Out
Signal: Timer Output
Logic.LE4.Out
Signal: Latched Output (Q)
Logic.LE4.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE4.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE4.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE4.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE5.Gate Out
Signal: Output of the logic gate
Logic.LE5.Timer Out
Signal: Timer Output
Logic.LE5.Out
Signal: Latched Output (Q)
Logic.LE5.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE5.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE5.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE5.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE6.Gate Out
Signal: Output of the logic gate
Logic.LE6.Timer Out
Signal: Timer Output
Logic.LE6.Out
Signal: Latched Output (Q)
Logic.LE6.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE6.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE6.Gate In4-I
State of the module input: Assignment of the Input Signal
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Содержание EDR-5000
Страница 63: ...EDR 5000 IM02602007E Ethernet RJ45 Terminal Marking www eaton com 63 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 253: ...EDR 5000 IM02602007E Fault Recorder Module Signals Signal Description Res record Signal Delete Record www eaton com 253...
Страница 887: ...EDR 5000 IM02602007E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 887...