EDR-5000
IM02602007E
Name
Description
Logic.LE35.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE35.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE35.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE36.Gate Out
Signal: Output of the logic gate
Logic.LE36.Timer Out
Signal: Timer Output
Logic.LE36.Out
Signal: Latched Output (Q)
Logic.LE36.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE36.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE36.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE36.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE37.Gate Out
Signal: Output of the logic gate
Logic.LE37.Timer Out
Signal: Timer Output
Logic.LE37.Out
Signal: Latched Output (Q)
Logic.LE37.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE37.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE37.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE38.Gate Out
Signal: Output of the logic gate
Logic.LE38.Timer Out
Signal: Timer Output
Logic.LE38.Out
Signal: Latched Output (Q)
Logic.LE38.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE38.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE38.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE38.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE38.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE38.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE39.Gate Out
Signal: Output of the logic gate
Logic.LE39.Timer Out
Signal: Timer Output
Logic.LE39.Out
Signal: Latched Output (Q)
Logic.LE39.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE39.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE39.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE39.Gate In3-I
State of the module input: Assignment of the Input Signal
www.eaton.com
991
Содержание EDR-5000
Страница 63: ...EDR 5000 IM02602007E Ethernet RJ45 Terminal Marking www eaton com 63 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 253: ...EDR 5000 IM02602007E Fault Recorder Module Signals Signal Description Res record Signal Delete Record www eaton com 253...
Страница 887: ...EDR 5000 IM02602007E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 887...