
EDR-5000
IM02602007E
Name
Description
Logic.LE52.Timer Out
Signal: Timer Output
Logic.LE52.Out
Signal: Latched Output (Q)
Logic.LE52.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE52.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE52.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE52.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE52.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE52.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE53.Gate Out
Signal: Output of the logic gate
Logic.LE53.Timer Out
Signal: Timer Output
Logic.LE53.Out
Signal: Latched Output (Q)
Logic.LE53.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE53.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE53.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE53.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE53.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE53.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE54.Gate Out
Signal: Output of the logic gate
Logic.LE54.Timer Out
Signal: Timer Output
Logic.LE54.Out
Signal: Latched Output (Q)
Logic.LE54.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE54.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE54.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE54.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE54.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE54.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE55.Gate Out
Signal: Output of the logic gate
Logic.LE55.Timer Out
Signal: Timer Output
Logic.LE55.Out
Signal: Latched Output (Q)
Logic.LE55.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE55.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE55.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE55.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE55.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE55.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE56.Gate Out
Signal: Output of the logic gate
Logic.LE56.Timer Out
Signal: Timer Output
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Содержание EDR-5000
Страница 63: ...EDR 5000 IM02602007E Ethernet RJ45 Terminal Marking www eaton com 63 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 253: ...EDR 5000 IM02602007E Fault Recorder Module Signals Signal Description Res record Signal Delete Record www eaton com 253...
Страница 887: ...EDR 5000 IM02602007E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 887...