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EDR-5000
IM02602007E
Name
Description
AR. 4
Abort the AR-cycle, if the state of the assigned signal is true. If the state of this function is true the AR will be
aborted.
AR. 5
Abort the AR-cycle, if the state of the assigned signal is true. If the state of this function is true the AR will be
aborted.
AR. 6
Abort the AR-cycle, if the state of the assigned signal is true. If the state of this function is true the AR will be
aborted.
Sync.Active
Signal: Active
Sync.ExBlo
Signal: External Blocking
Sync.LiveBus
Signal: Live-Bus flag: 1=Live-Bus, 0=Voltage is below the LiveBus threshold
Sync.LiveLine
Signal: Live Line flag: 1=Live-Line, 0=Voltage is below the LiveLine threshold
Sync.SynchronRunTiming
Signal: SynchronRunTiming
Sync.SynchronFailed
Signal: This signal indicates a failed synchronization. It is set for 5s when the breaker is still open after the
Synchron-Run-timer has timed out.
Sync.SyncOverridden
Signal:Synchronism Check is overridden because one of the Synchronism overriding conditions (DB/DL or
ExtBypass) is met.
Sync.VDiffTooHigh
Signal: Voltage difference between bus and line too high.
Sync.SlipTooHigh
Signal: Frequency difference (slip frequency) between bus and line voltages too high.
Sync.AngleDiffTooHigh
Signal: Phase Angle difference between bus and line voltages too high.
Sync.Sys-in-Sync
Signal: Bus and line voltages are in synchronism according to the system synchronism criteria.
Sync.In-Sync Allowed
Signal: In-Sync Allowed
Sync.ExBlo1-I
Module Input State: External Blocking1
Sync.ExBlo2-I
Module Input State: External Blocking2
Sync.Bypass-I
State of the module input: Bypass
Sync.BkrCloseInitiate-I
State of the module input: Breaker Close Initiate with synchronism check from any control sources (e.g. HMI /
SCADA). If the state of the assigned signal becomes true, a Breaker Close will be initiated (Trigger Source).
ECr.Cr Oflw VAh Net
Signal: Counter Overflow VAh Net
ECr.Cr Oflw Wh Net
Signal: Counter Overflow Wh Net
ECr.Cr Oflw Wh Fwd
Signal: Counter Overflow Wh Fwd
ECr.Cr Oflw Wh Rev
Signal: Counter Overflow Wh Rev
ECr.Cr Oflw VArh Net
Signal: Counter Overflow VArh Net
ECr.Cr Oflw VArh Lag
Signal: Counter Overflow VArh Lag
ECr.Cr Oflw VArh Lead
Signal: Counter Overflow VArh Lead
ECr.VAh Net Res Cr
Signal: VAh Net Reset Counter
ECr.Wh Net Res Cr
Signal: Wh Net Reset Counter
ECr.Wh Fwd Res Cr
Signal: Wh Fwd Reset Counter
ECr.Wh Rev Res Cr
Signal: Wh Rev Reset Counter
ECr.VArh Net Res Cr
Signal: VArh Net Reset Counter
ECr.VArh Lag Res Cr
Signal: VArh Lag Reset Counter
ECr.VArh Lead Res Cr
Signal: VArh Lead Reset Counter
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Содержание EDR-5000
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