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EDR-5000
IM02602007E
Name
Description
Logic.LE31.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE31.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE31.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE31.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE32.Gate Out
Signal: Output of the logic gate
Logic.LE32.Timer Out
Signal: Timer Output
Logic.LE32.Out
Signal: Latched Output (Q)
Logic.LE32.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE32.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE32.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE32.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE32.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE32.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE33.Gate Out
Signal: Output of the logic gate
Logic.LE33.Timer Out
Signal: Timer Output
Logic.LE33.Out
Signal: Latched Output (Q)
Logic.LE33.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE33.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE33.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE33.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE33.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE33.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE34.Gate Out
Signal: Output of the logic gate
Logic.LE34.Timer Out
Signal: Timer Output
Logic.LE34.Out
Signal: Latched Output (Q)
Logic.LE34.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE34.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE34.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE34.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE35.Gate Out
Signal: Output of the logic gate
Logic.LE35.Timer Out
Signal: Timer Output
Logic.LE35.Out
Signal: Latched Output (Q)
Logic.LE35.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE35.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE35.Gate In2-I
State of the module input: Assignment of the Input Signal
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Содержание EDR-5000
Страница 63: ...EDR 5000 IM02602007E Ethernet RJ45 Terminal Marking www eaton com 63 1 8 TxD TxD RxD N C N C RxD N C N C...
Страница 253: ...EDR 5000 IM02602007E Fault Recorder Module Signals Signal Description Res record Signal Delete Record www eaton com 253...
Страница 887: ...EDR 5000 IM02602007E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 887...