
EDR-5000
IM02602007E
Name
Description
Logic.LE64.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE64.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE64.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE64.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE64.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE65.Gate Out
Signal: Output of the logic gate
Logic.LE65.Timer Out
Signal: Timer Output
Logic.LE65.Out
Signal: Latched Output (Q)
Logic.LE65.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE65.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE65.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE65.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE65.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE65.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE66.Gate Out
Signal: Output of the logic gate
Logic.LE66.Timer Out
Signal: Timer Output
Logic.LE66.Out
Signal: Latched Output (Q)
Logic.LE66.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE66.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE66.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE66.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE66.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE66.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE67.Gate Out
Signal: Output of the logic gate
Logic.LE67.Timer Out
Signal: Timer Output
Logic.LE67.Out
Signal: Latched Output (Q)
Logic.LE67.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE67.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE67.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE67.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE67.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE67.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE68.Gate Out
Signal: Output of the logic gate
Logic.LE68.Timer Out
Signal: Timer Output
Logic.LE68.Out
Signal: Latched Output (Q)
Logic.LE68.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE68.Gate In1-I
State of the module input: Assignment of the Input Signal
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Содержание EDR-5000
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Страница 253: ...EDR 5000 IM02602007E Fault Recorder Module Signals Signal Description Res record Signal Delete Record www eaton com 253...
Страница 887: ...EDR 5000 IM02602007E Real Time Clock Running Reserve of the Real Time Clock 1 year min www eaton com 887...