2 MECHATROLINK-
III
Communications
2-6
2.3
Cyclic Communications Interrupt Processing
When the communications ASIC has been initialized, cyclic communications start between the master (host
controller) and slaves (SERVOPACKs). Refer to
5.2.2 Cyclic Communications Processing
in the
MECHA-
TROLINK-III Communication ASIC JL-100/JL-101 (C1 Master) Access Drivers
(Manual No.: MMA TDEP
024A)
for details on cyclic communications.
When cyclic communications start, the INT1 synchronized interrupt signal for cyclic communications is out-
put from the master and slave ASICs after the interrupt delay time (INToffset) from the transmission cycle
synchronization (SYNC) frame.
During interrupt processing, response data is read from the slave and processing related to that response data
(analysis of the response data and creation of command data to send to the slave) and user application process-
ing are performed after the communications ASIC’s communications buffer is switched.
The results of processing are written to the communication ASIC’s communications buffer as command data.
The command data must be written before the next INT1 synchronized interrupt signal for cyclic communica-
tions is input.
For synchronized interrupt processing, refer to the
mst_exchange_sync()
sample programming that is included
with the access drivers as an example and perform the following items.
• Confirm the communications ASIC status.
• Process switching the response data buffer and command data buffer.
• Confirm the response data reception status.
• Process the received response data (for all axes).
• Create the command data (for all axes).
• Write the command data (for all axes).