NO:
W90P710 Programming Guide
VERSION:
2.1
PAGE:
58
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
5 GDMA
5.1 Overview
The W90P710
GDMA
controller provides a data transfer mechanism without the need of CPU
intervention. It can move data between two memory regions, or between memory and external
devices. The GDMA has two independent channels that support single and block mode transfer.
When GDMA is programmed to
single
mode, it requires a request
(nXDREQ)
for each data transfer
that may be one byte, one half-word or one word. When GDMA is programmed to
block
mode, a
single GDMA request will make all of the data to be transferred.
The data transfer can be started after write the control register or receive an external DMA
request (nXDREQ). The GDMA will try to finish the data transfer according to the transfer mode,
source address, destination address and transfer count. The device driver can recognize the
completion of a GDMA operation by polling control register or when it receives a GDMA interrupt.
The W90P710 GDMA controller implements many flexible features to support the data transfers.
It can increment or decrement source or destination address during the data transfer, and conduct
with 8-bit (byte), 16-bit (half-word), or 32-bit (word) size data transfers. The source or destination
address of the GDMA can be fixed also. Furthermore, the GDMA supports 4-data burst mode to boost
performance and supports demand mode to speed up external GDMA operations.
