NO:
W90P710 Programming Guide
VERSION:
2.1
PAGE:
40
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
enabled at the same time. The write buffer can be enabled by setting the
WRBEN.
Most of the time,
ICAEN
,
DCAEN
and
WRBEN
are enabled at the same time.
3.4.5 Cache Load and Lock
The W90P710 cache controller supports a cache-locking feature that locks critical sections of
code or data into I-Cache or D-Cache. This guarantees the quick access to these critical sections.
Lockdown operation can be performed with a granularity of one cache line (4 words). The smallest
size, which can be locked down, is 4 words. After a line is locked, it operates as a regular instruction
SRAM. Locked lines don’t be replaced either cache misses or flush per line command. Figure 3-5
shows the steps for locking instructions or data.
Figure 3-3 Cache Load and Lock
Set CAHADR
Write the start address of the data
to be locked into CAHADR
register
Set CAHCON
1. Set LDLK.
2. Set ICAH for I-cache, DCAH
for D-cache
Increased the address
by 16
Desired data are all
locked ?
start
end
Yes
No
There are some limitations during the locking cache line into the I-Cache or D-Cache.
