NO:
W90P710 Programming Guide
VERSION:
2.0
PAGE:
216
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission
from Winbond.
Table No.: 2005-W90P710-11-A
PDR1
0xFFF8.7020
R
PWM Data Register 1
0000.0000
CNR2
0xFFF8.7024
R/W
PWM Counter Register 2
0000.0000
CMR2
0xFFF8.7028
R/W
PWM Comparator Register 2
0000.0000
PDR2
0xFFF8.702C
R
PWM Data Register 2
0000.0000
CNR3
0xFFF8.7030
R/W
PWM Counter Register 3
0000.0000
CMR3
0xFFF8.7034
R/W
PWM Comparator Register 3
0000.0000
PDR3
0xFFF8.7038
R
PWM Data Register 3
0000.0000
PIER
0xFFF8.703C
R/W
PWM Interrupt Enable Register
0000.0000
PIIR
0xFFF8.7040
R/C
PWM Interrupt Indication Register
0000.0000
19.4 Functional Description
19.4.1 Prescaler
and clock selector
W90P710 has two groups (two channels in each group) of pwm timers. The clock input of the
group is according to the PWM Prescaler Register (
PPR
) value. W90P710 PWM prescaler divided the
clock input by PPR+1 before it is fed to the counter. Please notice that when the PPR value equals
zero, the prescaler output clock will stop. Furthermore, according to the PWM Clock Select Register
(
CSR
) value, the clock input of PWM timer channel can be divided by 1,2,4,8 and 16.
Consider following examples, which explain the PWM timer period.
CSR
PPR
PCLK
÷
+
÷
=
)
1
(
)
(
1
period
When the PCLK=80 MHz, the maximum and minimum PWM timer counting period is described
as follows.
Maximum period: PPR=255(since the length of PPR is 8bit) and CSR=16
us
Mhz
2
.
51
16
)
1
255
(
)
80
(
1
period
max
=
÷
+
÷
=
Minimum period: PCLK=80 MHz, PPR=1 and CSR=1
