NO:
W90P710 Programming Guide
VERSION:
2.1
PAGE:
11
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
Table of Figures
Figure 1-1 W90P710 Functional Block Diagram ................................................................................ 16
Figure 2-1 SDRAM Interface............................................................................................................... 26
Figure 2-2 System Memory Map Setting Flow .................................................................................... 30
Figure 3-1 Instruction Cache Organization Block Diagram ................................................................. 36
Figure 3-2 Data Cache Organization Block Diagram .......................................................................... 37
Figure 3-3 Cache Load and Lock........................................................................................................ 40
Figure 4-1 EMC Block Diagram .......................................................................................................... 43
Figure 4-2 Rx Descriptor Initialization ................................................................................................. 47
Figure 4-3 Tx Descriptor Initialization.................................................................................................. 49
Figure 4-4 Packet Transmission Flow................................................................................................. 53
Figure 4-5 Tx Interrupt Service Routine Flow...................................................................................... 55
Figure 4-6 Rx Interrupt Service Routine.............................................................................................. 57
Figure 5-1 GDMA Block Diagram........................................................................................................ 59
Figure 5-2 The bit-fields of the GDMA control register........................................................................ 61
Figure 5-3 GDMA operations .............................................................................................................. 62
Figure 5-4 Software GDMA Transfer................................................................................................... 64
Figure 6-1 Endpoint Descriptor Format............................................................................................... 72
Figure 6-2 General Transfer Descriptor Format .................................................................................. 74
Figure 6-3 Isochronous Transfer Descriptor Format ........................................................................... 74
Figure 6-4 Remove an Endpoint Descriptor ........................................................................................ 79
Figure 6-5 ED list and TD queue......................................................................................................... 80
Figure 7-1 USBD Controller Block Diagram ........................................................................................ 95
Figure 10-2 USBD Controller Block Diagram ...................................................................................... 99
Figure 8-1 SDIO Host Block Diagram ............................................................................................... 103
Figure 9-1 LCD Controller Block Diagram......................................................................................... 108
Figure 9-2 Overall programming flow for LCD controller - 1.............................................................. 112
Figure 9-3 Overall programming flow for LCD controller - 2.............................................................. 114
Figure 9-4 The relationship between screen, valid window, and OSD window ................................. 117
Figure 9-5 An example to explain how to program the starting address and stride........................... 122
Figure 10-1 Block diagram of Audio Controlle................................................................................... 129
Figure 10-2 AC97 Playback Data in DMA Buffer .............................................................................. 135
