NO:
W90P710 Programming Guide
VERSION:
2.0
PAGE:
233
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission
from Winbond.
Table No.: 2005-W90P710-11-A
RESERVED
7
6
5
4
3
2
1
0
RESERVED TX_err
TX_IRQ
RESERVED
RX_IRQ
z
TX_IRQ
This
Transmit Complete Interrupt bit will be set to 1 if Host controller writing command to
device is finished. Software needs to write one to this bit to clear this interrupt.
z
RX_IRQ
This Receive Interrupt
bit will be set to 1 if Host controller receives one byte data from
device. This data is stored at PS2_SCANCODE register. Software needs to write one to
this bit to clear this interrupt after reading receiving data in RX_SCAN_CODE register.
Note that the reception of the Extend (0xE0) and Release (0xF0) scan code will not cause
an interrupt by host. The case of the shift key codes will be determined by the
TRAP_SHIFT bit of PS2_CMD register.
The following figure illustrates an example interrupt service routine.
Figure 21-4 Example ISR
