NO:
W90P710 Programming Guide
VERSION:
2.1
PAGE:
4
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
2.4.2
ROM/Flash control register............................................................................................ 28
2.4.3
SDRAM configuration registers ..................................................................................... 29
2.4.4
External I/O control registers ......................................................................................... 30
2.4.5
A system memory initialization example flow chart........................................................ 30
2.4.6
REMAPPING ................................................................................................................. 32
3
Cache Controller .......................................................................................................................... 35
3.1
Overview............................................................................................................................... 35
3.2
Block Diagram ...................................................................................................................... 36
3.3
Registers .............................................................................................................................. 38
3.4
Functional Descriptions ........................................................................................................ 38
3.4.1
On-Chip RAM ................................................................................................................ 38
3.4.2
Non-Cacheable Area ..................................................................................................... 39
3.4.3
Cache Flushing.............................................................................................................. 39
3.4.4
Cache Enable and Disable ............................................................................................ 39
3.4.5
Cache Load and Lock.................................................................................................... 40
3.4.6
Cache Unlock ................................................................................................................ 41
4
EMC (Ethernet MAC Controller) .................................................................................................. 42
4.1
Overview............................................................................................................................... 42
4.2
Block Diagram ...................................................................................................................... 43
4.3
Registers .............................................................................................................................. 44
4.3.1
EMC Control registers .................................................................................................. 44
4.3.2
EMC Status Registers ................................................................................................... 45
4.4
Functional Descriptions ........................................................................................................ 45
4.4.1
Initialize Rx Buffer Descriptors....................................................................................... 45
4.4.2
Initialize Tx Buffer Descriptors ....................................................................................... 48
4.4.3
MII ................................................................................................................................. 50
4.4.4
Control Frames.............................................................................................................. 52
4.4.5
Packet Processing......................................................................................................... 52
5
GDMA .......................................................................................................................................... 58
5.1
Overview............................................................................................................................... 58
5.2
Block Diagram ...................................................................................................................... 59
5.3
Registers .............................................................................................................................. 60
5.4
Functional Descriptions ........................................................................................................ 60
