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NO:

W90P710 Programming Guide

VERSION:

2.0

PAGE:

223

The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission
from Winbond.

Table No.: 2005-W90P710-11-A

20.2 Block Diagram

Figure 20-1 Keypad Controller Block Diagram

clock

dvider

prescalar

row

counter

8 : 3

encoder

row/column

buffer & control

Three_keys

buffers

&

debounce

counter

DBTC[7:0]

comparator

&

comparator

low power

wakeup

row scan

generation

&

STATUS

register

WAKEUP

register

EN3K

Y

ENR

S

T

CLOCK

15MHz

KPI_INT

KPI_RST

KPI_ROW

KPI_COL

KPI_WAKEUP

20.3 Register Map

Register

Address

R/W

Description

Reset Value

KPICONF

0xFFF8.8000

R/W

Keypad controller configuration Register

0x0000.0000

KPI3KCONF

0xFFF8.8004

R/W

Keypad controller 3-keys configuration register

0x0000.0000

KPILPCONF

0xFFF8.8008

R/W

Keypad controller low power configuration
register

0x0000.0000

KPISTATUS

0xFFF8.800C

R/O

Keypad controller status register

0x0000.0000

20.4 Functional Description

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Summary of Contents for W90P710

Page 1: ...1 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 1200 0003 07 A W90P...

Page 2: ...operty of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 1200 0003 07 A Revision History Revision Date Comment 1 0 08 30 2005 Initial...

Page 3: ...ller 19 1 1 7 USB Device Controller 19 1 1 8 SDIO Host Controller 19 1 1 9 LCD Controller 20 1 1 10 2 Channel AC97 I2S Audio Codec Host Interface 21 1 1 11 UART 21 1 1 12 Timers 21 1 1 13 Advanced Int...

Page 4: ...Overview 35 3 2 Block Diagram 36 3 3 Registers 38 3 4 Functional Descriptions 38 3 4 1 On Chip RAM 38 3 4 2 Non Cacheable Area 39 3 4 3 Cache Flushing 39 3 4 4 Cache Enable and Disable 39 3 4 5 Cache...

Page 5: ...ansfer 66 5 4 9 Demand Mode Transfer 66 6 USB Host Controller 68 6 1 Overview 68 6 2 Registers Map 69 6 3 Block Diagram 70 6 4 Data Structures 71 6 4 1 Endpoint Descriptor ED Lists 72 6 4 2 Transfer D...

Page 6: ...buffer 106 8 4 3 Move data from SDIO host controller buffer to SDRAM 106 8 5 SD Host Interface 106 8 5 1 Send Command to SD MMC Card 106 8 5 2 Get Response from SD MMC Card 107 8 5 3 SD MMC to Buffer...

Page 7: ...d AC97 Registers 132 10 4 3 Write AC97 Registers 134 10 4 4 AC97 Playback 135 10 4 5 AC97 Record 137 10 5 I2S Interface 138 10 5 1 I2S Play 138 10 5 2 I2S Record 140 11 UART 142 11 1 Overview 142 11 2...

Page 8: ...Priority Scheme 171 14 General Purpose Input Output GPIO 174 14 1 Overview 174 14 2 Register Map 176 14 3 Functional Description 177 14 3 1 Multiple Functin Setting 177 14 3 2 GPIO Output Mode 178 14...

Page 9: ...Transfer 202 17 4 4 Data Transfer 203 17 4 5 Below list Some Examples of I2C Data Transaction 203 18 Universal Serial Interface 209 18 1 Overview 209 18 2 Block Diagram 210 18 3 Register Map 210 18 4...

Page 10: ...0003 07 A 20 3 Register Map 223 20 4 Functional Description 223 20 4 1 KPI Interface Programming Flow 224 20 4 2 KPI Low Power Mode Configuration 225 21 PS 2 Host Interface Controller 227 21 1 Overvi...

Page 11: ...pt Service Routine 57 Figure 5 1 GDMA Block Diagram 59 Figure 5 2 The bit fields of the GDMA control register 61 Figure 5 3 GDMA operations 62 Figure 5 4 Software GDMA Transfer 64 Figure 6 1 Endpoint...

Page 12: ...ion Sequence 158 Figure 12 3 Timer Interrupt Service Routine 159 Figure 12 4 Enable Watchdog Timer 161 Figure 12 5 Watchdog Timer ISR 162 Figure 13 1 AIC block diagram 164 Figure 13 2 Source Control R...

Page 13: ...all not be disclosed distributed or reproduced without permission from Winbond Table No 1200 0003 07 A Figure 20 3 KPI set Wake Up in system low power mode flowchart 226 Figure 21 1 Key map of PS 2 ke...

Page 14: ...table 119 Table 9 5 STN 16 leve gray number relative Time based dithering 120 Table 9 6 BSWP 0 HSWP 0 125 Table 9 7 BSWP 0 HSWP 1 125 Table 9 8 BSWP 0 HSWP 0 125 Table 9 9 BSWP 1 HSWP 0 126 Table 10 1...

Page 15: ...tive applications The W90P710 offers a 4K byte I cache SRAM a 4K byte D cache SRAM and one MACs of Ethernet controller that reduces total system cost A color LCD controller is built in to support blac...

Page 16: ...roduced without permission from Winbond Table No 1200 0003 07 A Figure 1 1 W90P710 Functional Block Diagram On the following chapters programming note of each chapter will be described in detailed Cha...

Page 17: ...0003 07 A Chapter 8 SDIO Host Controller Chapter 9 LCD Controller Chapter 10 Audio Controller Chapter 11 UART Chapter 12 Timers Chapter 13 Advance Interrupt Controller Chapter 14 GPIO Chapter 15 Real...

Page 18: ...rnal Bus Interface 8 16 32 bit external bus support for ROM SRAM flash memory SDRAM and external I Os Support for SDRAM Programmable access cycle 0 7 wait cycle Four word depth write buffer Cost effec...

Page 19: ...in 8 bit 16 bit or 32 bit data transfers 4 data burst mode 1 1 6 USB Host Controller USB 1 1 compliant Compatible with Open HCI 1 0 specification Supports low speed and full speed devices Build in DMA...

Page 20: ...ts 4096 12bpp color for Color STN LCD panel Virtual coloring method Frame Rate Control 16 level Anti flickering method Time based Dithering TFT LCD Display Supports Sync type TFT LCD and Sync type Hig...

Page 21: ...ates 1 or 2 stop bits Odd or even parity Break generation and detection Parity overrun and framing error detection X16 clock mode Support for Bluetooth IrDA and Micro printer control 1 1 12 Timers Two...

Page 22: ...ode selectable Recognize leap year automatically Day of the week counter Frequency compensate register FCR Beside FCR all clock and alarm data expressed in BCD code Support tick time interrupt 1 1 16...

Page 23: ...ellation Start Stop Repeated Start Acknowledge generation Start Stop Repeated Start detection Bus busy detection Supports 7 bit addressing mode Software mode I2 C 1 1 18 Universal Serial Interface USI...

Page 24: ...t Programmable debounce time One or two keys scan with interrupt and three keys reset function Support low power mode wakeup function 1 1 21 PS2 Host Interface Controller APB slave consisted of PS2 pr...

Page 25: ...SH SDRAM and External I O devices The EBI has seven chip selects to select one ROM FLASH bank two SDRAM banks and four External I O banks and 25 bit address bus It supports 8 bit 16 bit and 32 bit ext...

Page 26: ...not be disclosed distributed or reproduced without permission from Winbond Table No 1200 0003 07 A 2 2 Block Diagram 2 2 1 SDRAM interface Figure 2 1 SDRAM Interface MCLK MCKE nSCS 1 0 nSRAS nSCAS nSW...

Page 27: ...rnal I O 2 control register 0x0000 0000 EXT3CON 0xFFF0 1024 R W External I O 3 control register 0x0000 0000 CKSKEW 0xFFF0 1F00 R W Clock skew control register for testing 0xXXXX 0038 2 4 Functional De...

Page 28: ...0 REFMOD 1 CLKEN 0 REFRAT don t care 2 4 2 ROM Flash control register ROM Flash control register is used to control the configuration of the boot ROM In this register the size base address access typ...

Page 29: ...the software has the responsibility to correct the setting boot up program should configure the of ROM Flash control register to let it work correctly after boot The ROM Flash interface is designed f...

Page 30: ...won t issue a mode register set command to SDRAM and the setting will be invalid The SDRAM controller offers auto pre charge mode of SDRAM for SDRAM bank0 1 If this mode is enabled the SDRAM will iss...

Page 31: ...s after remapping boot FLASH ROM base address Boot FLASH ROM 256KB 0x00000000 0x00040000 0x7FFFFFFF SDRAM BANK 1 0x00000000 0x02000000 SDRAM BANK 0 Boot FLASH ROM 256KB 0x04000000 0x7FFFFFFF Before In...

Page 32: ...this example is as Figure 2 4 In general the memory remapping only needs to be preformed once at reset Thus the reset value of SDCONF0 is used to check if the system has been initialized If the system...

Page 33: ...just paranoid MRS w1 cpsr BIC w1 w1 0x1F ORR w1 w1 0xD3 MSR cpsr_fc w1 Configure the EBI controller to remap the flash The EBI Control Registers must be set using store multiples Set up a stack in int...

Page 34: ...target values into the control registers ADRL r0 label SystemInitData LDMIA r0 r1 r6 LDR r0 EBICON Now run critical jump code STMIA r0 r1 r6 MOV pc lr label EndSysMapJump Now running from new PROM lo...

Page 35: ...f cache is enabled the CPU tries to fetch instructions from I cache instead of external memory Similarly the CPU tries to read data from D cache instead of external memory But note that the CPU will w...

Page 36: ...Diagram Figure 3 1 Instruction Cache Organization Block Diagram x x WS INDEX 7 0 1 2 3 4 10 11 30 31 Tag 20 Non cacheable Control bit L V Way1 Tag0 Way1 Tag1 Way1 Tag127 L V L V V L Way0 Tag0 Way0 Ta...

Page 37: ...A Figure 3 2 Data Cache Organization Block Diagram x x WS INDEX 7 0 1 2 3 4 10 11 30 31 Tag 20 Non cacheable Control bit L V Way1 Tag0 Way1 Tag1 Way1 Tag127 L V L V V L Way0 Tag0 Way0 Tag1 Way0 Tag12...

Page 38: ...R W Cache configuration register 0x0000 0000 CAHCON 0xFFF0 2004 R W Cache control register 0x0000 0000 CAHADR 0xFFF0 2008 R W Cache address register 0x0000 0000 3 4 Functional Descriptions 3 4 1 On C...

Page 39: ...d set bit will be cleared to 0 automatically The detail description of each bit filed can be found in W90P710 specification 3 4 3 Cache Flushing To prevent unpredictable error it s better to flush cac...

Page 40: ...D Cache This guarantees the quick access to these critical sections Lockdown operation can be performed with a granularity of one cache line 4 words The smallest size which can be locked down is 4 wor...

Page 41: ...ne and unlock all The unlock line operation is performed on a cache line granularity In case the line is found in the cache it is unlocked and starts to operate as a regular valid cache line In case t...

Page 42: ...on for Ethernet MAC address recognition Transmit FIFO Receive FIFO TX RX state machine controller and status controller The EMC only supports RMII Reduced MII interface to connect with PHY operating o...

Page 43: ...nbond Table No 1200 0003 07 A 4 2 Block Diagram Figure 4 1 EMC Block Diagram AHB Bus Master AHB Bus Slave Register Files MII Management State Machine MDC MDIO TxDMA State Machine RxDMA State Machine T...

Page 44: ...W CAM6 Least Significant Word Register 0x0000 0000 CAM7M 0xFFF0 3040 R W CAM7 Most Significant Word Register 0x0000 0000 CAM7L 0xFFF0 3044 R W CAM7 Least Significant Word Register 0x0000 0000 CAM8M 0...

Page 45: ...R W Missed Packet Count Register 0x0000 7FFF MRPC 0xFFF0 30BC R MAC Receive Pause Count Register 0x0000 0000 MRPCC 0xFFF0 30C0 R MAC Receive Pause Current Count Register 0x0000 0000 MREPC 0xFFF0 30C4...

Page 46: ...roperty of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 1200 0003 07 A 6 The start address of descriptor and data buffer are sugges...

Page 47: ...escriptors Write the start address of allocated Rx Buffer Descriptors to RXDLSA also initialized Rx software pointer Set ownership bits of each descriptor to DMA Allocate memory for Rx data buffers 4...

Page 48: ...and let Tx software pointer point to this address 3 Set ownership bits of each descriptor to CPU 4 Allocate memory to save frame data and write the address to data buffer start address field of Tx des...

Page 49: ...ated Tx Buffer Descriptors to TXDLSA also initialized Tx software pointer Set ownership bits of each descriptor to CPU Allocate memory for Tx data buffers 4 Bytes boundary and write the address of dat...

Page 50: ...6 Read data from MIID register 7 Finish the read command 1 Write data to MIID register 2 Set appropriate MDCCR 3 Set PHYAD and PHYRAD 4 Set Write to 1 b1 5 Set bit BUSY to 1 b1 to send a MII manageme...

Page 51: ...xt page available 13 Remote fault 10 Flow control support 09 100BASE T4 support 08 100BASE TX full duplex support 07 100BASE TX half duplex support 06 10BASE T full duplex support 05 10BASE T half dup...

Page 52: ...1 Fill the destination MAC address to CAM 13 2 Fill the source MAC address to CAM 14 3 Fill length type 0x8808 opcode 0x0001 and operand timeslot to CAM 15 4 Set SDPZ bit in MCMDR 5 Wait control paus...

Page 53: ...Buffer Descriptor Pointer Check ownership bits CPU Run out of Descriptors Exception Handling Allocate data buffer for storing transmitting packets set the start address of data buffer to Data Buffer...

Page 54: ...2 Tx Interrupt Service Routine 1 Get and check status in MISTA 2 Set software reset bit in FIFOTHD and re initialize MAC if bus error occur Do the following step if no error occur 3 Get status from t...

Page 55: ...terrupt Service Routine Flow Check status of MISTA Bus Error Set Software Reset bit in FIFOTHD to reset MAC Get Status from Tx Buffer Descriptor pointed by Tx S W pointer TXCP bit set Free data buffer...

Page 56: ...t software reset bit in FIFOTHD and re initialize MAC if bus error occur Do the following step if no error occur 3 Get ownership from the descriptor of Rx software pointer Do the following step if own...

Page 57: ...ror RXGD Copy the received data to buffer provided by upper protocol layer Change ownership bits to DMA Update the Rx S W descriptor pointer to next descriptor Rx S W Descriptor pointer the same as CR...

Page 58: ...k mode a single GDMA request will make all of the data to be transferred The data transfer can be started after write the control register or receive an external DMA request nXDREQ The GDMA will try t...

Page 59: ...Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 1200 0003 07 A 5 2 Block Diagram Figure 5 1 GDMA Block Diagram GDMA Channel 0 nDREQ nD...

Page 60: ...ter 0x0000 0000 GDMA_CTL1 0xFFF0 4020 R W Channel 1 Control Register 0x0000 0000 GDMA_SRCB1 0xFFF0 4024 R W Channel 1 Source Base Address Register 0x0000 0000 GDMA_DSTB1 0xFFF0 4028 R W Channel 1 Dest...

Page 61: ...stination base address register GDMA_DSTB is used to set the starting address where the source data to be stored The number of the GDMA transfer is set by programming the transfer count register GDMA_...

Page 62: ...direction fixing bust bus lock transfer width block mode interrupt are set here Clear TC Transfer complete End Clean control register Set source address If the SOFTREQ was not self clean in the previ...

Page 63: ...ration to continue 5 4 4 GDMA operation started by software The GDMA can be configured as software mode to perform memory to memory transfer In this mode the transfer operation starts as soon as the s...

Page 64: ...gs SABNDERR and DABNDERR will be set Figure 5 4 shows an example code for software GDMA transfer Figure 5 4 Software GDMA Transfer d e f i n e B A S E 0 x c 0 0 0 0 0 0 0 d e f i n e G D M A _ S R C B...

Page 65: ...completed the current source destination and transfer count status can be read from current status registers These current status registers are GDMA_CSRC GDMA_CDST and GDMA_CTNT respectively However...

Page 66: ...the bit SOFTREQ is set the GDMA begins to transfer data After the numbers of data specified on register GDMA_TCNT have been transferred the GDMA set the bit TC and generates an interrupt if it is enab...

Page 67: ...ed without permission from Winbond Table No 1200 0003 07 A When nXDREQ is active and GDMA gets the bus in Demand mode GDMA controller holds the system bus until the nXDREQ signal becomes non active Th...

Page 68: ...eripheral devices The attached peripherals share USB bandwidth through a host scheduled token based protocol Peripherals may be attached configured used and detached while the host and other periphera...

Page 69: ...er 0x0000 0000 HcBulkCurrentED 0xFFF0 502C R W Host Controller Bulk Current ED Register 0x0000 0000 HcDoneHead 0xFFF0 5030 R W Host Controller Done Head Register 0x0000 0000 HcFmInterval 0xFFF0 5034 R...

Page 70: ...shall not be disclosed distributed or reproduced without permission from Winbond Table No 1200 0003 07 A 6 3 Block Diagram USB Host Controller USB Interface Host Controller AHB Interface AHB Slave AH...

Page 71: ...e communication method for HC initiated communication with the Host Controller Driver There are several events that may trigger an interrupt from the Host Controller Each specific event sets a specifi...

Page 72: ...st Controller fulfills USB transfers by classifying Endpoints into four types of Endpoint Descriptor lists The Control ED list is pointed by HcControlHeadED register the Bulk ED list is pointed by HcB...

Page 73: ...s polling interval Interrupt ED list which is also a part of each Interrupt ED list You may have no any 1ms polling interval Interrupt EDs in some of the real scenes If it was the case then you will h...

Page 74: ...3 Buffer End BE Figure 6 3 Isochronous Transfer Descriptor Format 3 2 2 2 2 2 2 2 1 1 1 1 0 0 0 1 8 7 6 4 3 1 0 6 5 2 1 5 4 0 Dword 0 CC FC DI SF Dword 1 Buffer Page 0 BP0 Dword 2 NextTD 0 Dword 3 Buf...

Page 75: ...able 6 1 HCCA Host Controller Communication Area Offset Size bytes Name Description 0 128 HccaInterrruptTable These 32 Dwords are pointers to interrupt EDs 0x80 2 HccaFrameNumber Contains the current...

Page 76: ...ue of HostControllerReset become 0 3 Allocate and create all necessary list structures and memory blocks including HCCA and initialize all driver maintained lists including InterruptTable of HCCA Note...

Page 77: ...AIC Advanced Interrupt Controller USB interrupt which is IRQ9 13 Connect Hub device driver 6 5 2 USB States The Host Controller has four USB states visible to the Host Controller Driver via the Operat...

Page 78: ...state Conditions USBRESET Hardware Reset USBRESET USBOPERATIONAL Writing 0x2 to HostControllerFunctionalState USBSUSPEND 1 Writing 0x3 to HostControllerFunctionalState 2 Issue a Software Reset command...

Page 79: ...t ED in an ED list The NextED of the last Endpoint Descriptor must points to zero to signify the end of an ED list To add an Endpoint Descriptor to an ED list HCD should write physical address of the...

Page 80: ...figured as empty In Figure 10 2 the HeadP and TailP pointer of last ED has pointed to the same Transfer Descriptor that is the TD queue of this ED is empty The TD there under the ED is a dummy TD Whil...

Page 81: ...follow the following steps to remove a TD 1 Modify the HeadP pointer of the Endpoint Descriptor HC always service the first TD of the TD queue to link to the next TD HC can obtain the link of the next...

Page 82: ...can clear Halted bit and enable processing on the endpoint again 6 5 5 IRP Processing The data structure of IRP is operation system dependent Host Controller driver should be able to interpret the con...

Page 83: ...P is 9KB then HCD will generate three TDs for this IRP Because OHCI handles the data toggles by itself it just deed to set the toggle bits for the first TD The data toggle setting of the subsequent TD...

Page 84: ...ating system several isochronous packets to be transferred may be carried in a single IRP HCD must prepare appropriate Isochronous TDs for these isochronous packets For example in Linux s implementati...

Page 85: ...Head to HccaDoneHead On this interrupt HCD can obtain the TD done queue by reading HccaDoneHead HCD may first reverse the done queue by traveling the done queue because the TDs were retired in stack o...

Page 86: ...this interrupt when it detects a system error not related to USB or an error that cannot be reported in any other way HCD may try to reset Host Controller in this case 6 5 6 6 FrameNumberOverflow Inte...

Page 87: ...wing is an example implementation of Host Controller interrupt service routine VOID hc_interrupt int vector OHCI_T ohci _W90P710 _OHCI OHCI_REGS_T regs ohci regs INT ints _InUsbInterrupt 1 ints ohci r...

Page 88: ...e Done Queue is built by the Host Controller and referred to by the HcDoneHead register No matter successful or failed the retired Transfer Descriptors must be put into the Done Queue by Host Controll...

Page 89: ...st_hc if TD_CC_GET UINT32 td_list hwINFO urb_priv URB_PRIV_T td_list urb hcpriv TD_CompletionCode TD_CC_GET UINT32 td_list hwINFO if td_list ed hwHeadP 0x1 if urb_priv td_list index 1 urb_priv length...

Page 90: ...may collect data received by Host Controller or do nothing it depends on the implementation In addition to invoke complete routine HCD may release the IRP or re submit the IRP if it is the Interrupt T...

Page 91: ...te 1 to bit 16 to turn off power to all ports ClearRemoteWakeupEnable write 1 to bit 31 to disable device remote wakeup In addition the HcRhStatus register also indicates the following status OverCurr...

Page 92: ...ableStatus bit 1 indicate whether the port is enabled or disabled PortSuspendStatus bit 2 indicate the port is suspended or not PortResetStatus bit 4 indicate the Root Hub is asserting reset signal on...

Page 93: ...ntercepted Refer to the following code static INT sohci_submit_urb URB_T urb some code assertted here handle a request to the virtual root hub if usb_pipedevice pipe ohci rh devnum return rh_submit_ur...

Page 94: ...use as described below z EP0 the default endpoint uses control transfer In Out to handle configuration and control functions required by the USB specification Maximum packed size is 16 bytes z EPA de...

Page 95: ...0x0000 0000 USB_VCMD 0xFFF0 6004 R W USB class or vendor command register 0x0000 0000 USB_IE 0xFFF0 6008 R W USB interrupt enable register 0x0000 0000 USB_IS 0xFFF0 600C R USB interrupt status registe...

Page 96: ...NFO 0xFFF0 6064 R W USB endpoint B information register 0x0000 0000 EPB_CTL 0xFFF0 6068 R W USB endpoint B control register 0x0000 0000 EPB_IE 0xFFF0 606C R W USB endpoint B Interrupt Enable register...

Page 97: ...mand decode 5 Set bits RST_ENDI and RSTI of USB_IE register to enable the reset interrupt 6 Set bits CDII and CDOI of USB_IE register to enable the control data in and control data out interrupt 7 Set...

Page 98: ...g 0x20400012 to register EPB_INFO Note This configuration must be consistent with configuration interface and endpoint descriptors 2 Enable endpoint interrupts by configure register EPx_IE according t...

Page 99: ...inpw REG_USB_EPB_IS if Irq USB_EPB_DMA USB_ISR_EPB_DMA_Complete else if Irq inpw REG_USB_EPC_IS if Irq USB_EPC_DMA USB_ISR_EPC_DMA_Complete else if Note If Reset End interrupt is generated ISR must cl...

Page 100: ...TAx 2 Parse vendor command 3 Set flag according to the command 4 Set bit SDO_RD of USB_ENG 1 Get data from USB_ODATAx according to the command get in previous interrupt 2 Parse data of class or vendor...

Page 101: ...ecute the relative sub interrupt service routine 5 The control data in FIFO is the registers USB_IDATA0 USB_IDATA3 total 16 bytes If the device descriptor length is over 16 bytes the programmer should...

Page 102: ...al the USBD hardware such as interrupt enable refer to initialization section 10 4 1 4 After finish the above steps plug the USBD into the host 5 The host will ask the descriptors such as device confi...

Page 103: ...IO Host Controller of W90P710 supports Secure Digital interface This interface can directly connect to MMC SD SDIO cards The SDIO host controller also supports DMA function to reduce the intervention...

Page 104: ...ital Interface Control Signals Data Path Address Path 8 3 Registers Register Offset R W Description Reset Value FMI Registers 6 SDGCR 0xFFF0 7000 R W SD Global Control Register 0x0000 0000 SDDSA 0x FF...

Page 105: ...0 0x FFF0 75FC R W Flash Buffer 0 Undefined FB1_0 FB1_127 0x FFF0 7800 0x FFF0 79FC R W Flash Buffer 1 Undefined 8 4 SDIO Host Controller Accessing data through SDIO host controller interface takes tw...

Page 106: ...ISR register 8 4 3 Move data from SDIO host controller buffer to SDRAM 1 Set RdSel bit of SDGCR register to select buffer for use Set 000 is use buffer0 and set 100 is use buffer1 2 Set SDBCR register...

Page 107: ...1 2 Set SDBLEN register to 0x1FF One block is 512 bytes The value of this register should be count 1 3 Send READ_SINGLE_BLOCK command to the card 4 Set DI_EN bit of SDICR register to enable data input...

Page 108: ...ission from Winbond Table No 1200 0003 07 A 9 LCD Controller 9 1 1 Overview The main purpose of LCD Controller is used to display the video OSD raw data to external display device It supports common p...

Page 109: ...g Guide VERSION 2 1 PAGE 109 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Ta...

Page 110: ...r count register 0000 0000 FIFO2DREQCNT 0xFFF0 803C R W FIFO2 data request transfer count register 0000 0000 FIFO1CURADR 0xFFF0 8040 R FIFO1 current access address 0000 0000 FIFO2CURADR 0xFFF0 8044 R...

Page 111: ...0000 0000 LCD Timing Generation LCDTCON1 0xFFF0 80B0 R W LCD Timing Control Register1 0000 0000 LCDTCON2 0xFFF0 80B4 R W LCD Timing Control Register2 0000 0000 LCDTCON3 0xFFF0 80B8 R W LCD Timing Cont...

Page 112: ...disclosed distributed or reproduced without permission from Winbond Table No 1200 0003 07 A 9 1 2 Programming Procedure This section describes the software programming flow for LCD controller Follow...

Page 113: ...DINTENB LCDINTC Use OSD function Yes Configure OSD function OSDOVCN OSDKYP OSDKYM Configure LCD Timing Generatio n LCDTCON 1 LCDTCON 2 LCDTCON 3 LCDTCON 4 LCDTCON 5 LCDTCON 6 No Use STN pane l Yes Con...

Page 114: ...ing flow for LCD controller 2 B Configure the starting address and the stride of frame buffer and FIFO FIFO1PRM FIFO2PRM F1 SADDR F2 SADDR F1 DREQCNT F2 DREQCNT F1 REALCULCNT F2 REALCULCNT Configure h...

Page 115: ...LCD Controller The user can configure the common settings of this controller by programming register LCDCON Function of each field is explained as Table 9 2 Table 9 2 Register LCDCON Bit Map Register...

Page 116: ...o LCD uses 8 bit interface 5 TFT Type Select 0 Sync type High Color TFT LCD 1 Sync type TFT LCD 4 LCD is TFT 0 LCD is an STN display 1 LCD is a TFT display 3 STN LCD is monochrome 0 STN LCD is color 1...

Page 117: ...ead Status register and write Clear register HSYNC interrupt FIFO2 VLINE FINISH interrupt and FIFO1 VLINE FINISH interrupt are only for debug Don t use these interrupts under normal environment The pr...

Page 118: ...OSD data can be transparent blinking or mixed with video data by setting overlay control register The display condition is depicted in the following table Table 9 3 OSD Display Condition OSDEN Color K...

Page 119: ...SDKYM 2 Decide Video Synthesis Weighting OSDOVCN 6 4 3 Configure Video OSD overlay control 0 and 1 OSDOVCN 3 0 4 Enable Color Key Control OSDOVCN 8 5 If blinking function is desired Configure Blinking...

Page 120: ...2 9 9 3 9 9 9 4 9 9 9 9 5 9 9 9 9 9 6 9 9 9 9 9 9 7 9 9 9 9 9 9 9 8 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 9 9 9 9 9 9 9 9 9 9 11 9 9 9 9 9 9 9 9 9 9 9 12 9 9 9 9 9 9 9 9 9 9 9 9 13 9 9 9 9 9 9 9 9 9...

Page 121: ...aling function is required configure register OSD Up scaling Factor OSDUPSCF 3 Go to Step 6 4 If the Video down scaling function is required configure register Video Down scaling Factor VDDNSCF 5 If t...

Page 122: ...cessing address Column counter counts the FIFO writing pulse If Horizontal Up Scaling factor is 2X FIFO will extract a pixel data to two pixel data internal So if Horizontal Up Scaling function is ena...

Page 123: ...n from Winbond Table No 2005 W90P710 11 A 2 120 pixels 480 pixels 480 pixels 3 240 pixels 1 60 pixels If there is an image with size 480 480 24bpp stored in memory device with starting address is 0x30...

Page 124: ...FIFO Real Column Count is the same with FIFO Column Count But if horizontal down scaling function is enabled factor M is not equal with N FIFO Real Column Count specify the column count of original im...

Page 125: ...OSDWINS and OSDWINE 9 12Enable FIFO It contains two 16 words FIFO When LCD FIFO is enabled and there are no data in FIFO LCD FIFO will generate a request to LCD Arbiter After FIFO is full of data LCD...

Page 126: ...eo or OSD raw data is swap format set the swap control bits FIFOCON 19 16 2 If only video data is inputted enable FIFO1 FIFOCON 0 if video and OSD raw data are both inputted enable FIFO1 and FIFO2 FIF...

Page 127: ...lusive intellectual property of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A LCDINTS 5 0 3 Set the flags and clea...

Page 128: ...rface with external audio CODEC One 8 level deep FIFO for read path and write path and each level has 32 bit width 16 bits for right channel and 16 bits for left channel One DMA controller handle the...

Page 129: ...nd shall not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A 10 2Block Diagram Figure 10 1 Block diagram of Audio Controlle AHB Bus Master AHB Bus Sla...

Page 130: ...000 0000 ACTL_PDSTC 0xFFF0 9020 R DMA destination current address register for play 0x0000 0000 ACTL_PSR 0xFFF0 9024 R W Play status register 0x0000 0004 ACTL_IISCON 0xFFF0 9028 R W IIS control regist...

Page 131: ...le 10 2 AC97 Output Frame Data Format Tag slot 0 Bit 15 frame validity bit 1 is valid 0 is invalid Bits 14 3 slot validity but in W99702 only bits 6 3 are used bits 14 7 are unused Bit 3 is correspond...

Page 132: ...te Audio mode Bit 10 PCM data for right channel request Bit 9 0 should be cleared to 0 Status DATA Slot 2 Bit 19 4 Control register read data which previous frame requested It should be cleared to 0 i...

Page 133: ...e written to ACTL_ACOS1 If the echo value was not correct check the hardware 7 Read AC97 register value from RD 15 0 of ACTL_ACIS2 register A sample code is given below static UINT16 ac97_read_registe...

Page 134: ...VALID 0 and SLOT_VALID 1 bits of ACTL_ACOS0 register The register index will be delivered by slot1 and setting value will be delivered by slot2 4 Polling the AC_W_FINISH bit of ACTL_ACCON register unt...

Page 135: ...AC97 codec It supports single channel or 2 channels transfer The data arrangement in playback DMA buffer was shown in the following figure Figure 10 2 AC97 Playback Data in DMA Buffer DMA buffer 2 cha...

Page 136: ...CTL_RESET_BIT bit of ACTL_RESET register high for 10ms to reset W90P710 audio controller And pull AC_RESET bit of ACTL_RESET register high for 10ms to reset W90P710 AC97 interface 4 Reset the external...

Page 137: ...0x10007 Right channel MSB byte DMA buffer 1 channel 0x10000 Left channel LSB byte 0x10001 Left channel MSB byte 0x10002 Left channel LSB byte 0x10003 Left channel MSB byte 0x10004 Left channel LSB by...

Page 138: ...END_IRQ bit was set read PCM data from the second half of record DMA buffer Once enough PCM data has been gathered and recording wants to be stopped just clear the AC_RECORD bit of ACTL_RESET register...

Page 139: ...04 Left channel LSB byte 0x10005 Left channel MSB byte 0x10006 Left channel LSB byte 0x10007 Left channel MSB byte Note The DMA buffer is double buffering It will trigger an interrupt when half length...

Page 140: ...Left channel MSB byte 0x10002 Right channel LSB byte 0x10003 Right channel MSB byte 0x10004 Left channel LSB byte 0x10005 Left channel MSB byte 0x10006 Right channel LSB byte 0x10007 Right channel MS...

Page 141: ...sampling rate of the external codec through L3 interface 5 Set the bit 3 ACTL_IISCON to determine the data format And set the data format of external codec through L3 W99P710 support two formats of I...

Page 142: ...terrupt for device driver to control the transmitting operation receiving operation and error handling There are five types of interrupts including line status interrupt transmitter FIFO empty interru...

Page 143: ...Divisor Latch Register LS DLAB 1 0x0000 0000 UART1_DLM 0xFFF8 0104 R W Divisor Latch Register MS DLAB 1 0x0000 0000 UART1_IIR 0xFFF8 0108 R Interrupt Identification Register 0x8181 8181 UART1_FCR 0xFF...

Page 144: ...Interrupt Identification Register 0x8181 8181 UART3_FCR 0xFFF8 0308 W FIFO Control Register Undefined UART3_LCR 0xFFF8 030c R W Line Control Register 0x0000 0000 UART3_MCR 0xFFF8 0310 R W Modem Contr...

Page 145: ...eal Error rate 115200 0 6 117187 5 1 725 57600 0 14 58593 75 1 725 38400 0 22 39062 5 1 725 19200 0 47 19132 65 0 35 9600 0 96 9566 33 0 35 11 3 2 Initializations Before the transfer operation starts...

Page 146: ...ess Bit 6 BCB Break Control Bit 5 SPE Stick Parity Bit 4 EPE Even Parity Enable 3 PBE Parity Bit Enable 2 NSB Number of STOP bit 0 One STOP bit 1 1 5 STOP bit 1 0 WLS Word Length Select 00 5 bits 01 6...

Page 147: ...k UART buffer by reading status register If there s at least one data byte available in receive FIFO the RFDR bit is set 1 It indicates that driver can read receive FIFO to get new data bytes If the t...

Page 148: ...The interrupt service routine is responsible to move data bytes from driver s buffer to transmit FIFO whenever the THRE interrupt happens If RDA or TOUT interrupts occurs the interrupt service routin...

Page 149: ...Winbond Table No 2005 W90P710 11 A from Rx FIFO the driver receiving buffer when the receiver threshold level reaching interrupt occurs When the input function is called it reads the data bytes from...

Page 150: ...ectronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A Start Write one data byte to driver s buffer Is buffer available for another d...

Page 151: ...y of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A Start Is there at least one data byte in driver s buffer Read o...

Page 152: ...11 6 Interrupt Service Routine Start ReadISR Is THRE Interrupt Move data bytes from driver buffer to Tx FIFO Is data byte available in driver s buffer Disable THRE interrupt Is RDA or TOUT interrupt R...

Page 153: ...while receiving and vice versa The IrDA SIR physical layer specifies a minimum 10ms transfer delay between transmission and reception This feature should be implemented by software Figure 11 7 IrDA T...

Page 154: ...assert an interrupt request if the interrupt is enabled A general software counting scheme is to set a software counter and add 1 to it upon every interrupt The Timer module also includes a watchdog t...

Page 155: ...TISR 8 BIT PRESCALE 24 BIT COUNTER 8 BIT PRESCALE 24 BIT COUNTER 24 BIT COUNTER TINT0 TINT0 WDTINT WDTRST TIMER 0 TIMER 1 WATCHDOG TIMER TOUT0 TOUT1 58 6KHz 15MHz AMBA APB Interface 12 3Registers R r...

Page 156: ...n the following equation Freq Crystal clock pre scaler 1 counter For W90P710 the crystal clock input is 15 MHZ According to the equation user can decide the values of pre scalar and counter to get the...

Page 157: ...nd shall not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A In periodic mode the interrupt signal is generated periodically In toggle mode the interr...

Page 158: ...thout permission from Winbond Table No 2005 W90P710 11 A Figure 12 2 Timer Initialization Sequence Start Disable Timer Set Operating Mode Prescaler Set Counter Enable Timer End Clear CE and IE of TCRx...

Page 159: ...ce Routine A common timer interrupt service routine is very simple It increases the software counter and clears the timer interrupt status Figure 12 3 shows the flow chart of such an interrupt service...

Page 160: ...be set before enable watchdog timer It ensures that the watchdog timer restarts from a known state Figure 12 4 and Figure 12 5 illustrate how to use watchdog timer Table 12 2 list the WatchDog Timeou...

Page 161: ...sion from Winbond Table No 2005 W90P710 11 A Figure 12 4 Enable Watchdog Timer Start Reset WatchDog Timer Select Time Out Interval and Enable WatchDog Timer End Program WTR bit by 1 to WTCR to reset t...

Page 162: ...buted or reproduced without permission from Winbond Table No 2005 W90P710 11 A Figure 12 5 Watchdog Timer ISR Start Clear Interrupt Flag and Reset WatchDog Timer End WTCR Register 3 WTIF WatchDog Time...

Page 163: ...ARM7TDMI only if there s at least one interrupt channel is active and enabled The software driver can implement a priority scheme based on the status register However the AIC itself implements a prop...

Page 164: ...Table No 2005 W90P710 11 A 13 2Block Diagram Figure 13 1 AIC block diagram A I C _ C T R L R e c o r d e r A I C _ I R E C E n c o d e r A I C _ I E N C s t a t u s m a s k r s ta t u s s ta t u s n...

Page 165: ...00 0047 AIC_SCR10 0xFFF8 2028 R W Source Control Register 10 0x0000 0047 AIC_SCR11 0xFFF8 202C R W Source Control Register 11 0x0000 0047 AIC_SCR12 0xFFF8 2030 R W Source Control Register 12 0x0000 00...

Page 166: ...00 AIC_IASR 0xFFF8 2104 R Interrupt Active Status Register 0x0000 0000 AIC_ISR 0xFFF8 2108 R Interrupt Status Register 0x0000 0000 AIC_IPER 0xFFF8 210C R Interrupt Priority Encoding Register 0x0000 00...

Page 167: ...rtinent interrupt type according to the external devices The priority level of each interrupt channel is completely decided by the interrupted device After power on or reset all the channels are assig...

Page 168: ...pt status has been was cleared the AIC de asserts the interrupt request For the interrupt channels that are edge triggered the device driver must clear AIC status to de assert the interrupt request To...

Page 169: ...not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A executed firstly Then it will call the proper interrupt service routine according to the AIC_ISR c...

Page 170: ...perty of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A Figure 13 3 Sequential Priority Scheme Start Read AIC_ISR M...

Page 171: ...the interrupt channel number that is active enabled and has the highest priority multiplied by 4 then stored on the AIC_IPER The data Vector got from AIC_IPER is convenient for the following interrup...

Page 172: ..._Handler jump to the correct handler LDR R2 AICBase LDR R1 R2 AIC_IPER gets the highest pending vector LDR PC PC R1 jump to correct handler NOP table of handler start address DCD Fake_Interrupt DCD In...

Page 173: ...EOSCR to restore to normal interrupt state once it read the AIC_IPER Otherwise the next interrupt may not be serviced correctly Figure 13 5 shows the programming flow of using hardware priority scheme...

Page 174: ...d as I O port Two extended interrupts nIRQ4 GPIO0 pin and nIRQ5 nWAIT pin are used the same interrupt request channel 31 of AIC It can be programmed as low high sensitive or positive negative edge tri...

Page 175: ...8 SC0_CLK SD_CLK VD16 9 GPIO29 SC0_DAT SD_CMD VD17 PORT2 Configuration Pin Functions 0 GPIO42 PHY_RXERR KPCOL0 1 GPIO43 PHY_CRSDV KPCOL1 2 GPIO44 PHY_RXD 0 KPCOL2 3 GPIO45 PHY_RXD 1 KPCOL3 4 GPIO46 PH...

Page 176: ...41 VD7 KPCOL7 14 2Register Map Register Address R W Description Reset Value GPIO_CFG0 0xFFF8 3000 R W GPIO port0 configuration register 0x0000 0000 GPIO_DIR0 0XFFF8 3004 R W GPIO port0 direction contr...

Page 177: ...O_DIR6 0XFFF8 3064 R W GPIO port6 direction control register 0x0000 0000 GPIO_DATAOUT6 0xFFF8 3068 R W GPIO port6 data output register 0x0000 0000 GPIO_DATAIN6 0xFFF8 306C R GPIO port6 data input regi...

Page 178: ...ut register GPIO_DATAOUTn Programmer should not change the value of whole register except the corresponding field of the register A sample code set GPIO PORT0 pin1 as GPIO output then change the outpu...

Page 179: ...e GPIO_DIRn OMDENx y value as 0 input mode After the above steps user can get the GPIO pin input value high or low by read the GPIO data input register GPIO_DATAINn A sample code set GPIO PORT0 pin1 a...

Page 180: ...Guide VERSION 2 0 PAGE 180 The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Tabl...

Page 181: ...erate 32 768KHz clock The RTC can transmit data to CPU as BCD values The data include the time by second minute hour and the date by day month year In addition to reach better frequency accuracy the R...

Page 182: ...r alarm counter Day of the week counter 1 Day FCR Compensate frequency by software Tick interrupt generator XTALIN XTALOUT Alarm Tick interrupt Select one Tick period 15 3Register Map Register Address...

Page 183: ...tion When RTC block is power on programmer has to write a number Oxa5eb1357 to register INIR to reset all logic INIR act as hardware reset circuit Once INIR has been set as 0xa5eb1357 user cannot relo...

Page 184: ...te Register Value Describtion AER 0 RTC read write disable CLR 05 1 1 2005 1 1 TLR 00 00 00 00 hr 00 min 00 sec CAR 00 00 00 2000 0 0 TAR 00 00 00 00 hr 00 min 00 sec TSSR 1 24 hr mode DWR 6 Saturday...

Page 185: ...16 2 0x10 FCR 5 0 0x10 z In TLR and TAR only 2 BCD digits are used to express year We assume 2 BCD digits of XY denote 20XY but not 19XY or 21XY 15 5Programming Note 15 5 1 1 Set Calendar and Time 1...

Page 186: ...produced without permission from Winbond Table No 2005 W90P710 11 A Figure 15 2 RTC Set Calendar and Time flow chart RTC start Initialize RTC INIR Initialize completed bit 0 of INIR be high Enable reg...

Page 187: ...ut permission from Winbond Table No 2005 W90P710 11 A 15 5 2 Set Calendar and Time Alarm 1 Set and prepare the ISR of RTC alarm 2 Set time and calendar same as above step 1 8 3 Set alarm year month an...

Page 188: ...ond Table No 2005 W90P710 11 A Figure 15 3 RTC Set Calendar and Time Alarm flow chart RTC start INitialize RTC INIR Initilaize copleted bit 0 of INIR be high Enable register R W AER Enable register R...

Page 189: ...block is power on programmer has to write a number 0xa5eb1357 to INIR to reset all logic RTC 3 Read register INIR bit 0 if INIR16 equals to 1 means RTC has been set 4 Write 0xa965 to AER means enable...

Page 190: ...all not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A RTC start Initialize RTC INIR Initialize completed bit 0 of INIR be high Enable register R W A...

Page 191: ...SO 7816 compliant z PC SC T 0 T 1 compliant z 16 byte transmitter FIFO and 16 byte receiver FIFO z FIFO threshold interrupt to optimize system performance z Programmable transmission clock frequency z...

Page 192: ..._0 0xFFF8 5034 R W Time out Initial Register 2 0x0000 0000 SCHI_TOD0_0 0xFFF8 5038 R Time out Data Register 0 0x0000 00FF SCHI_TOD1_0 0xFFF8 503C R Time out Data Register 1 0x0000 00FF SCHI_TOD2_0 0xF...

Page 193: ...ter 0x0000 001F SCHI_BLH1 0xFFF8 5804 BDLAB 1 R W Baud Rate Divisor Latch Higher Byte Register 0x0000 0000 SCHI_ID1 0xFFF8 5808 BDLAB 1 R Smart Card ID Number Register 0x0000 0070 16 3Functional Descr...

Page 194: ...timer2 respectively in time out configuration register SCHI_TOC The five operation modes are listed below 1 Mode 0 3b 000 Timer is stopped 2 Mode 1 3b 001 Timer starts counting the value stored in ti...

Page 195: ...the same mode value to SCHI_TOC can t trigger the same timer again so must change to Mode 0 before triggering the same mode 4 Current bug when reading register SCHI_SCSR time out flag can t be clean...

Page 196: ...with 0x2580 9600 0x2580 12 Configure TOC 5 3 in register SCHI_TOC with 3b 010 13 During ATR transmission if TO1 in register SCHI_SCSR is set a initial waiting time error has been detected 14 Once the...

Page 197: ...ed The interrupt notifies host to read data from FIFO A new incoming data word or receiver FIFO empty clear this interrupt 16 3 4 Parity Error management The error character in reception or in transmi...

Page 198: ...er FIFO In transmission 1 If a transmitted character has been NACK by the card then our smart card host interface will automatically re transmit it a number of times equal to the value programmed in P...

Page 199: ...100kbps and 400kbps modes are supported directly For High speed mode special IOs are needed If these IOs are available and used then High speed mode is also supported Data is transferred between a Ma...

Page 200: ...d distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A Arbitration lost interrupt with automatic transfer cancellation Start Stop Repeated Start Acknowledge generation...

Page 201: ...PB Interface Clock Prescale I2C Core Logic 17 3Register Map Register Address R W Description Reset value I2C Interface 0 I2C_CSR0 0xFFF8 6000 R W Control and Status Register 0x0000 0000 I2C_DIVIDER0 0...

Page 202: ...ister must be programmed to this 5 SCL frequency minus 1 Change the value of the prescale register only when the I2C_EN bit is cleared Example pclk 32MHz desired SCL 100KHz 3 63 1 100 5 32 hex F dec K...

Page 203: ...id data after the IF flag has been set The software may issue a new write or read command when the I2C_TIP flag is cleared 17 4 5 Below list Some Examples of I2C Data Transaction 17 4 5 1 Write One By...

Page 204: ...to TxR register TxR 15 8 5 Write data 0xAC to TxR register TxR 7 0 6 Set START bit STOP bit and WRITE bit of CMDR register 7 Wait for interrupt or I2C_TIP flag to negate 8 Read I2C_RxACK bit of CSR r...

Page 205: ...high byte 0x12 to TxR register TxR 15 8 and address low byte 0x34 to TxR register TxR 7 0 5 Set START bit and WRITE bit of CMDR register 6 Wait for interrupt or I2C_TIP flag to negate 7 Read I2C_RxACK...

Page 206: ...ad S Slave Address 7 b 1001110 R W A f rommastertoslav e f romslav etomaster A acknowledge SDA low A not acknowledge SDAhigh S START condition P STOP condition Commands 1 Write a value into DIVIDER re...

Page 207: ...Generate start signal 2 Write slave address write bit then receive acknowledge from slave 3 Write memory location then receive acknowledge from slave 4 Generate repeated start signal 5 Write slave add...

Page 208: ...ss read bit 1 to TxR 7 0 8 Set START bit and WRITE bit of CMDR register 9 Wait for interrupt or I2C_TIP flag to negate 10 Read I2C_RxACK bit from CSR register it should be 0 If it is not 0 there are s...

Page 209: ...level of device slave select signal can be chosen to low active or high active which depends on the peripheral it s connected Writing a divisor into DIVIDER register can program the frequency of seria...

Page 210: ...w_so_o mw_si_i pclk preset_n paddr pwrite psel penable pwdata pben prdata I O Decoder Registers Clock Generator Tx Rx Buffer MICROWIRE SPI Core Logic AMBA APB Interface Pin descriptions mw_sclk_o USI...

Page 211: ...ansmit Register 0 0x0000 0000 USI_Tx1 0xFFF8 6214 W Data Transmit Register 1 0x0000 0000 USI_Tx2 0xFFF8 6218 W Data Transmit Register 2 0x0000 0000 USI_Tx3 0xFFF8 621C W Data Transmit Register 3 0x000...

Page 212: ...2 Set USI_SSR register to select the access device 3 Set LSB bit of USI_CNTRL register to send LSB or MSB first 4 Set the IE bit of USI_CNTRL register to enable Universal Serial Interface interrupt 18...

Page 213: ...and can be used to handle one PWM period The 16 bit comparator compares number in counter with threshold number in register loaded previously to generate PWM duty cycle The clock signal from clock div...

Page 214: ...ion from Winbond Table No 2005 W90P710 11 A The value of comparator is used for pulse width modulation The counter control logic changes the output level when down counter value matches the value of c...

Page 215: ...Control logic pwm_clk CMR CNR CMR Dead zone generator Dead zone Dead zone 19 3Register Map Register Address R W C Description Reset Value PPR 0xFFF8 7000 R W PWM Prescaler Register 0000 0000 CSR 0xFFF...

Page 216: ...R C PWM Interrupt Indication Register 0000 0000 19 4Functional Description 19 4 1 Prescaler and clock selector W90P710 has two groups two channels in each group of pwm timers The clock input of the gr...

Page 217: ...0MHz Therefore all of the values need to be recalculated when the PCLK is not equal to 80Mhz 19 4 2 Basic PWM timer operation and double buffering reload automatically W90P710 PWM Timers have a double...

Page 218: ...R 50 151 51 200 50 Reg_CNR 199 Reg_CMR 49 Reg_CNR 99 Reg_CMR 0 100 1 Reg_CNR 0 Reg_CMR XX Stop PWM double buffering 19 4 3 PWM Timer Start Procedure The PWM Timer start procedure is is described as fo...

Page 219: ...disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A Figure 19 3 PWM Timer Start Procedure PWM Timer Start Setup prescaler dead zone interval PPR Setup clock...

Page 220: ...e Three different methods could used to stop PWM timer they re listed below Method 1 Set 16 bit down counter CNRx as 0 and monitor PDR When PDRx reaches to 0 disable pwm timer PCR Recommended Method 2...

Page 221: ...ty of Winbond Electronics and shall not be disclosed distributed or reproduced without permission from Winbond Table No 2005 W90P710 11 A Figure 19 5 PWM Timer Stop flow chart method 2 PWM running Set...

Page 222: ...ys are pressed only the keys or apparent keys in the array with the lowest address will be decoded KPI supports 2 keys scan interrupt and specified 3 keys interrupt or chip reset If the 3 pressed keys...

Page 223: ...s debounce counter DBTC 7 0 comparator comparator low power wakeup row scan generation STATUS register WAKEUP register EN3KY ENRST CLOCK 15MHz KPI_INT KPI_RST KPI_ROW KPI_COL KPI_WAKEUP 20 3Register M...

Page 224: ...nbond Table No 2005 W90P710 11 A 20 4 1 KPI Interface Programming Flow The KPI usage procedure is described as follows 1 Install KPI interrupt service routine 2 Configure GPIO KPI Multiple function 3...

Page 225: ...wchart 20 4 2 KPI Low Power Mode Configuration When the system enters power down or idle mode user can use KPI interrupt to wake up it Programming need to set WAKE bit and configure LPWCEN 15 8 and LP...

Page 226: ...R means binary code For example if user wants to use all keys on row 3 of 16x8 keyapd to wakeup W90P710 then 0x3 should be fill into this register but for 4x8 keypad it should be filled as 4 b1000 and...

Page 227: ...es the host controller provides a command register for software driver to send commands to keyboard Some devices implementing PS 2 protocol can be connected to this host controller For example the BAR...

Page 228: ...11 A Figure 21 2 Key map of extended keyboard Numeric keypad Although most set two make codes are only one byte wide there are a handfull of extended keys whose make codes are two or four bytes wide T...

Page 229: ...Register Map The PS 2 interface host controller provides four control registers The regisger PS2CMD is used to send command to a PS 2 device The register PS2STS indicates the status of transmit and re...

Page 230: ...Set Status LED s This command can be used to turn on and off the Num Lock Caps Lock Scroll Lock LED s After Sending ED keyboard will reply with ACK FA and wait for another byte which determines their...

Page 231: ...tend 7 6 5 4 3 2 1 0 RX_SCAN_CODE z RX_release When one key has been released the keyboard will send its break code that is preceded by a data byte 0xF0 to host controller This bit indicates software...

Page 232: ...ED 23 22 21 20 19 18 17 16 RESERVED 15 14 13 12 11 10 9 8 RESERVED 7 6 5 4 3 2 1 0 RX_ASCII_CODE z RX_ASCII_CODE This field stores the ASCII data content transmitted from device Therefore this part tr...

Page 233: ...d Software needs to write one to this bit to clear this interrupt z RX_IRQ This Receive Interrupt bit will be set to 1 if Host controller receives one byte data from device This data is stored at PS2_...

Page 234: ...mission from Winbond Table No 2005 W90P710 11 A START END Read register PS2STS Is RX_IRQ 1 A scan code arrived 1 Set a software envent 2 Read registers PS2SCANCODE PS2ASCII Is TX_IRQ 1 A command has b...

Page 235: ...nting 1 to the corresponding interrupt bits 21 4 5 Example This example tells that how to turn on off the LEDs on the keyboard if host controller receives the scan codes including 0x77 Num Lock 0x58 C...

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