NO:
W90P710 Programming Guide
VERSION:
2.0
PAGE:
155
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission
from Winbond.
Table No.: 2005-W90P710-11-A
12.2 Block Diagram
Figure 12-1 Timer Block Diagram
PCLK
PWRITE
PENABLE
PSEL
PADDR[31:0]
PRDATA[31:0]
PWDATA[31:0]
PRESETn
15 MHz
TCLK0
TCLK1
WTCLK
TCR0
TICR0
TDR0
TCR1
TICR1
TDR1
WTCR
TISR
8-BIT PRESCALE
24-BIT COUNTER
8-BIT PRESCALE
24-BIT COUNTER
24-BIT COUNTER
TINT0
TINT0
WDTINT
WDTRST
TIMER 0
TIMER 1
WATCHDOG TIMER
TOUT0
TOUT1
58.6KHz/15MHz
A
M
B
A
A
P
B
I
n
te
rf
a
ce
12.3 Registers
R
: read only,
W
: write only,
R/W
: both read and write,
C
: Only value 0 can be written
Register
Address
R/W/C Description
Reset Value
TCR0
0xFFF8.1000 R/W
Timer Control Register 0
0x0000.0005
TCR1
0xFFF8.1004 R/W
Timer Control Register 1
0x0000.0005
TICR0
0xFFF8.1008 R/W Timer Initial Control Register 0
0x0000.0000
TICR1
0xFFF8.100C R/W
Timer Initial Control Register 1
0x0000.0000
TDR0
0xFFF8.1010 R
Timer Data Register 0
0x0000.0000
