NO:
W90P710 Programming Guide
VERSION:
2.0
PAGE:
168
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission
from Winbond.
Table No.: 2005-W90P710-11-A
enable the corresponding interrupt channel. Oppositely, the
Mask Disable Command Register
(AIC_MDCR)
is used to disable the interrupt. Write 1 to a bit of MDCR will disable the corresponding
interrupt channel. Write 0 to a bit of AIC_MECR or AIC_MDCR has no effect. Therefore, the device
driver can arbitrarily change these two registers without keeping their original values. If it’s necessary,
the device driver can read the
Interrupt Mask Register (AIC_IMR)
to know whether the interrupt
channel is enabled or disabled. If the interrupt channel is enabled, its corresponding bit is read as 1,
otherwise 0.
13.4.3
Interrupt Clearing and Setting
For the interrupt channels that are level sensitive, the device driver doesn’t need to write the
Source Clear Command Register (AIC_SCCR)
or
End of Service Command Register
(AIC_EOSCR) to
clear any AIC status. As soon as the device’s interrupt status has been was cleared,
the AIC de-asserts the interrupt request. For the interrupt channels that are edge-triggered, the device
driver must clear AIC status to de-assert the interrupt request. To clear AIC status, the device driver
may either write
Source Clear Command Register (AIC_SCCR)
or
End of Service Command
Register (AIC_EOSCR)
. Write 1 to a bit of AIC_SCCR will clear the corresponding interrupt. The
usage of AIC_EOSCR will be discussed in the section
Hardware Priority Scheme
.
The register
Source Set Command Register (AIC_SSCR)
is used to active an interrupt channel
when it is programmed to edge-triggered. Write 1 to a bit of AIC_SSCR will set the corresponding
interrupt. This feature is useful in auto-testing or software debugging.
13.4.4 Software
Priority
Scheme
The AIC provides an
Interrupt Status Register (AIC_ISR)
to identify the interrupt sources. If an
interrupt channel is both active and enabled, its corresponding bit in AIC_ISR is set as 1. The interrupt
handler of FIQ or IRQ can get the interrupt sources by reading AIC_ISR. And the service sequence is
completely decided by software algorithm.
Generally, there’s a function table to keep the interrupt service routines of internal peripherals and
external devices. When the interrupt is recognized by CPU core, the FIQ or IRQ exception handler is