NO:
W90P710 Programming Guide
VERSION:
2.0
PAGE:
202
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission
from Winbond.
Table No.: 2005-W90P710-11-A
I2C_SWR1
0xFFF8.610C
R/W
Software Mode Control Register
0x0000.003F
I2C_RxR1
0xFFF8.6110
R
Data Receive Register
0x0000.0000
I2C_TxR1
0xFFF8.6114
R/W
Data Transmit Register
0x0000.0000
17.4 Functional Description
17.4.1 Prescale
Frequency
It is used to prescale the SCL clock line. Due to the structure of the I
2
C interface, the core uses a
5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1).
Change the value of the prescale register only when the
I2C_EN
bit is cleared.
Example: pclk = 32MHz, desired SCL = 100KHz
)
(
3
)
(
63
1
100
5
32
hex
F
dec
KHz
MHz
prescale
=
=
−
∗
=
17.4.2
Start and Stop Signal
The I
2
C core generates a START signal when the START bit in register CMDR is set
and the READ or WRITE bits are also set. Depending on the current status of the SCL
line, a START or Repeated START is generated.
The I
2
C core generates a STOP signal when the STOP bit in the register CMDR is set
and the READ or WRITE bits are also set.
17.4.3
Slave Address Transfer
The core treats a Slave Address Transfer as any other write action. Store the slave device’s
address in the register
TxR
and set the
WRITE
bit in
CMDR
register. The core will then transfer the
slave address on the bus.
