NO:
W90P710 Programming Guide
VERSION:
2.0
PAGE:
171
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission
from Winbond.
Table No.: 2005-W90P710-11-A
13.4.5 Hardware
Priority
Scheme
The AIC implements a proprietary 8-level priority scheme. To use this mechanism, the proper
AIC_SCRx should be programmed before enable the interrupt channels. Similarly, the FIQ or IRQ
exception handler is executed firstly when the interrupt is recognized. The exception handler and
interrupt service routine should follow certain rules to let this mechanism work correctly. The rules are
listed below.
1. Reads IRQ Priority Encoding Register (AIC_IPER) to get the Vector (IRQ Channel x 4),
and at this mean time, the AIC_ISNR will be loaded by the current interrupt channel
number, the Vector (IRQ Channel Number x 4) represents the interrupt channel number
that is active, enabled, and has the highest priority, multiplied by 4, then stored on the
AIC_IPER. The data (Vector) got from AIC_IPER is convenient for the following interrupt
service route address calculation. enabled, and has the highest priority.
2. Branch to the corresponding interrupt service routine by adding Vector to the base of
interrupt service routine table.
3. Write any value to AIC_EOSCR to finish the interrupt.
The priority level of the interrupt channel that is active and enabled is treated as
current priority
level
. It is pushed into the
Priority Encoder
when AIC_IPER is read. In the same time, the AIC_ISNR
was loaded by the current encoded interrupt channel number. This prevents AIC from asserting an
interrupt request if the following active and enabled interrupt has lower priority level. Therefore, the
interrupt service routine must write AIC_EOSCR to pop the current priority level from priority Encoder
to let AIC service the interrupt channel with lower priority. This hardware priority control is helpful to
implement a nesting interrupt system.
