NO:
W90P710 Programming Guide
VERSION:
2.1
PAGE:
38
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
3.3 Registers
R
: read only,
W
: write only,
R/W
: both read and write,
C
: Only value 0 can be written
Register
Address
R/W
Description
Reset Value
CAHCNF
0xFFF0.2000
R/W Cache
configuration
register
0x0000.0000
CAHCON
0xFFF0.2004 R/W
Cache
control register
0x0000.0000
CAHADR
0xFFF0.2008
R/W
Cache address register
0x0000.0000
3.4 Functional Descriptions
3.4.1 On-Chip RAM
If I-Cache or D-Cache is disabled, it can be used as On-Chip SRAM. The size of On-Chip RAM
depends on the I-Cache and D-Cache enable bits
ICAEN
,
DCAEN
in Cache Configuration Register
(CAHCNF)
. The details listed in Table 3-1.
Table 3-1 The size and start address of On-Chip RAM
ICAEN DCAEN
On-Chip RAM
Size
Start Address
0 0
8KB 0x7FE0.0000
0 1
4KB 0x7FE0.0000
1 0
4KB 0x7FE0.1000
1 1
Unavailable
