NO:
W90P710 Programming Guide
VERSION:
2.0
PAGE:
163
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed, distributed or reproduced without permission
from Winbond.
Table No.: 2005-W90P710-11-A
13 AIC (Advanced Interrupt Controller)
13.1 Overview
The W90P710 incorporates the
advanced interrupt controller (AIC)
that is capable of dealing
with the interrupt requests from 32 different interrupt sources. Currently, 31 interrupt sources are
defined. Each interrupt source is uniquely assigned to an
interrupt channel (1 to 31)
. Every interrupt
channel can be enabled or disabled individually. A channel is treated as active if its corresponding
interrupt source has an interrupt request. Several status registers are used to distinguish the state of
these interrupt channels. The AIC will assert an interrupt request to CPU core (ARM7TDMI) only if
there’s at least one interrupt channel is active and enabled.
The software driver can implement a priority scheme based on the status register. However, the
AIC itself implements a proprietary eight-level priority scheme to improve the interrupt dispatch time. It
differentiates the available 31 interrupt sources into eight priority levels, level 0 is the highest one and
the level 7 is the lowest. Within each priority level, a lower channel number interrupt source has a
higher priority. The AIC will assert the FIQ request if the active and enabled interrupt channel is
assigned to priority level 0. For the interrupt channels that are assigned to other priority level, AIC will
assert an IRQ request. The IRQ can be preempted by the occurrence of the FIQ. Interrupt nesting is
performed automatically by the AIC.
Although the internal interrupt sources of W90P710 are intrinsically high-level sensitive, the driver
can configure each interrupt source to be either low-level sensitive, high-level sensitive, negative-
edge triggered, or positive-edge triggered.
