NO:
W90P710 Programming Guide
VERSION:
2.1
PAGE:
35
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
3 Cache
Controller
3.1 Overview
The W90P710 incorporates a 4KB Instruction cache, a 4KB Data cache, and 8 words write buffer
to improve the system performance. The caches consist of high-speed SRAM that provides quicker
access time than external memory. If cache is enabled, the CPU tries to fetch instructions from I-
cache instead of external memory. Similarly, the CPU tries to read data from D-cache instead of
external memory. But note that the CPU will write data into both D-cache and write buffer (
write-
through
mode). If I-Cache / D-Cache were disabled, these cache memories can be treated as On-
Chip SRAM.
To raise the cache-hit ratio, these two caches are configured as two-way set associative
addressing. Both I-cache and D-Cache organization is 256 sets, two lines per set. Each cache has four
words cache line size. When a miss occurs, four words must be fetched consecutively from external
memory. The replacement algorithm is a LRU (Least Recently Used).
