NO:
W90P710 Programming Guide
VERSION:
2.1
PAGE:
71
The above information is the exclusive intellectual property of Winbond Electronics and shall not be disclosed,
distributed or reproduced without permission from Winbond.
Table No.: 1200-0003-07-A
The master issues the address and data onto the bus when granted.
AHB Slave
The configuration of the
Host Controller
is through the slave interface.
List Processing
The List Processor manages the data structures from the
Host Controller Driver
and
coordinates all activities within the
Host Controller
.
Frame Management
Frame Management is responsible for managing the frame specific tasks required by the USB
specification and the OpenHCI specification.
Interrupt Processing
Interrupts are the communication method for HC-initiated communication with the
Host
Controller Driver
. There are several events that may trigger an interrupt from the
Host
Controller
. Each specific event sets a specific bit in the
HcInterruptStatus
register.
Host Controller Bus Master
The
Host Controller
Bus Master is the central block in the data path. The
Host Controller
Bus
Master coordinates all access to the AHB Interface. There are two sources of bus mastering
within
Host Controller
: the List Processor and the Data Buffer Engine.
Data Buffer
The Data Buffer serves as the data interface between the Bus Master and the SIE. It is a
combination of a 64-byte latched based bi-directional asynchronous FIFO and a single Dword
AHB Holding Register.
6.4 Data Structures
Except direct access to
Host Controller
by registers,
Host Controller Driver
must maintain the
following memory blocks to communicate with
Host Controller
:
•
Endpoint Descriptor
Lists
