User Manual of A90 Series Inverter
72
51: switching of main frequency
source to digital frequency setting
52: switching of main frequency
source to AI1
53: Switching of main frequency
source to AI2
54: retention
55: retention
56: switching of main frequency
source to communication setting
57: inverter enabling
58-68: retention
69: prohibit reversing
165: switching of main frequency
to VP
F02.15
Positive/negative
logic 1 of digital input
terminal
D7 D6 D5 D4 D3 D2 D1 D0
*00
00000
○
*
*
* X5 X4 X3 X2 X1
0: positive logic is valid in the
closed state/invalid in the open
state
1: negative logic is valid in the
closed state/invalid in the open
state
F02.16
Positive/negative
logic 2 of digital
input terminal
D7 D6 D5 D4 D3 D2 D1
D
0
000
00000
○
*
*
*
*
*
* AI2
AI
1
0: positive logic is valid in the
closed state/invalid in the open
state
1: negative logic is valid in the
closed state/invalid in the open
state
F02.17
Filtering times of
digital input terminal
0-100; 0: no filtering; n: sampling
every n ms
2
○
F02.18 X1 valid delay time
0.000~30.000
s
0.000
●
F02.19 X1 invalid delay time 0.000~30.000
s
0.000
●
F02.20 X2 valid delay time
0.000~30.000
s
0.000
●
F02.21 X2 invalid delay time 0.000~30.000
s
0.000
●
F02.22 X3 valid delay time
0.000~30.000
s
0.000
●
F02.23 X3 invalid delay time 0.000~30.000
s
0.000
●
F02.24 X4 valid delay time
0.000~30.000
s
0.000
●
F02.25 X4 invalid delay time 0.000~30.000
s
0.000
●
