11 16-BiT PWM TiMeR (T16a2)
11-12
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
8.2 Internal Clock Division Ratio Selection
Table 11.
T16aClKD[3:0]
Division ratio
Clock source = OSC3B
Clock source = OSC1a
0xf
Reserved
0xe
1/16384
Reserved
0xd
1/8192
Reserved
0xc
1/4096
Reserved
0xb
1/2048
Reserved
0xa
1/1024
Reserved
0x9
1/512
Reserved
0x8
1/256
0x7
1/128
0x6
1/64
0x5
1/32
0x4
1/16
0x3
1/8
0x2
1/4
0x1
1/2
0x0
1/1
(Default: 0x0)
D[3:2]
T16aClKSRC[1:0]: Clock Source Select Bits
Selects the count clock source.
8.3 Clock Source Selection
Table 11.
T16aClKSRC[1:0]
Clock source
0x3
External clock (EXCL
x
)
0x2
Reserved
0x1
OSC1A
0x0
OSC3B
(Default: 0x0)
When using an external clock as the count clock, supply the clock to the EXCL
x
pin.
D1
Reserved
D0
T16aClKe: Count Clock enable Bit
Enables or disables the count clock supply to the counter.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
The T16ACLKE default setting is 0, which disables the clock supply. Setting T16ACLKE to 1 sends
the clock selected as above to the counter. If timer operation is not required, disable the clock supply to
reduce current consumption.
T16a Counter Ch.
x
Control Register (T16a_CTl
x
)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
T16a Counter
Ch.
x
Control
Register
(T16a_CTl
x
)
0x5400
(16 bits)
D15–7
–
reserved
–
–
–
0 when being read.
D6
hCM
Half clock mode enable
1 Enable
0 Disable
0
R/W
D5–4
–
reserved
–
–
–
0 when being read.
D3
CBuFen
Compare buffer enable
1 Enable
0 Disable
0
R/W
D2
TRMD
Count mode select
1 One-shot
0 Repeat
0
R/W
D1
PReSeT
Counter reset
1 Reset
0 Ignored
0
W 0 when being read.
D0
PRun
Counter run/stop control
1 Run
0 Stop
0
R/W
D[15:7] Reserved
D6
hCM: half Clock Mode enable Bit
Sets T16A2 to half clock mode.
1 (R/W): Enabled (half clock mode)
0 (R/W): Disabled (normal clock mode) (default)
Setting HCM to 1 places T16A2 into half clock mode. In half clock mode, T16A2 uses the dual-edge
counter, which counts at the rising and falling edges of the count clock, to generate a compare A signal
when the dual-edge counter value matches the T16A_CCA
x
register. This makes it possible to control
the duty ratio with double accuracy as compared to normal clock mode.
