8 Real-TiMe ClOCK (RTC)
8-6
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
D8
RTCST: RTC Run/Stop Status Bit
Indicates the RTC operating status.
1 (R):
Running
0 (R):
Stop (default)
RTCST goes 1 when the RTC starts running by writing 1 to RTCRUN. RTCST reverts to 0 when the
count operation is actually stopped after 0 is written to RTCRUN. When setting counter values, write 0
to RTCRUN and make sure that RTCST is reset to 0 before writing data.
D[7:6]
Reserved
D5
BCDMD: BCD Mode Select Bit
Sets the second, minute, and hour counters into BCD mode.
1 (R/W): BCD mode
0 (R/W): Binary mode (default)
By default, each counter operates as a binary counter and a binary value is read or written as counter
data. Setting BCDMD to 1 configures the counter so that two-digit BCD value can be read or written.
See Section 8.2 for the configuration of the counter in each mode.
D4
RTC24h: 24h/12h Mode Select Bit
Selects whether to use the hour counter in 24-hour or 12-hour mode.
1 (R/W): 24-hour mode
0 (R/W): 12-hour mode (default)
The count range of the hour counter changes with this selection. Basically, this setting should be
changed while the counters are idle. Since this register is assigned a control bit (D0) to start the coun-
ters, 12-hour or 24-hour mode may be selected when starting the counters.
D[3:1]
Reserved
D0
RTCRun: RTC Run/Stop Control Bit
Starts or stops the RTC.
1 (R/W): Start
0 (R/W): Stop (default)
The RTCRUN default setting is 0, which stops the RTC. Setting RTCRUN to 1 enables the CLG to send
the clock to the RTC. When RTCRUN is set to 1, the OSC1A oscillator circuit does not stop even if the
IC enters SLEEP mode (the OSC1A clock will be supplied to the RTC only).
Writing 1 to RTCRUN resets the OSC1A divider in the CLG module.
RTC interrupt enable Register (RTC_ien)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
RTC interrupt
enable Register
(RTC_ien)
0x56c2
(16 bits)
D15–10
–
reserved
–
–
–
0 when being read.
D9
inT1Den
1-day interrupt enable
1 Enable
0 Disable
0
R/W
D8
inThDen
Half-day interrupt enable
1 Enable
0 Disable
0
R/W
D7
inT1hen
1-hour interrupt enable
1 Enable
0 Disable
0
R/W
D6
inT10Men
10-minute interrupt enable
1 Enable
0 Disable
0
R/W
D5
inT1Men
1-minute interrupt enable
1 Enable
0 Disable
0
R/W
D4
inT10Sen
10-second interrupt enable
1 Enable
0 Disable
0
R/W
D3
inT1hZen
1 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D2
inT4hZen
4 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D1
inT8hZen
8 Hz interrupt enable
1 Enable
0 Disable
0
R/W
D0
inT32hZen
32 Hz interrupt enable
1 Enable
0 Disable
0
R/W
This register is used to enable/disable RTC interrupts. When the interrupt enable bit for an interrupt cycle is set to
1, the corresponding interrupt flag will be set to 1 in the interrupt cycles and the interrupt request will be sent to the
ITC. If an interrupt enable bit is set to 0, the interrupt request will not be sent to the ITC.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
D[15:10] Reserved
