
18 SuPPlY VOlTaGe DeTeCTiOn CiRCuiT (SVD)
18-4
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
SVD Detection Result Register (SVD_RSlT)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
SVD Detection
Result Register
(SVD_RSlT)
0x5102
(8 bits)
D7–1
–
reserved
–
–
–
0 when being read.
D0
SVDDT
SVD detection result
1 Low
0 Normal
×
R
D[7:1]
Reserved
D0
SVDDT: SVD Detection Result Bit
Indicates the power supply voltage detection results.
1 (R):
Power supply voltage (V
DD
) < comparison voltage
0 (R):
Power supply voltage (V
DD
)
≥
comparison voltage
The SVD circuit compares the power supply voltage (V
DD
) against the voltage set in SVDC[4:0]/SVD_
CMP register while SVDEN/SVD_EN register = 1. The current power supply voltage status can be
monitored by reading SVDDT. Also the detection result is set to SVDDT by writing 0 to SVDEN, so
the power supply voltage status can be checked by reading SVDDT after that.