7 ClOCK GeneRaTOR (ClG)
7-2
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
ClG input/Output Pins
7.2
Table 7.2.1 lists the input/output pins for the CLG module.
2.1 List of CLG Pins
Table 7.
Pin name
i/O
Qty
Function
OSC1
I
1
OSC1A oscillator input pin
Connect a crystal resonator (32.768 kHz) and a gate capacitor.
OSC2
O
1
OSC1A oscillator output pin
Connect a crystal resonator (32.768 kHz) and a drain capacitor.
FOUTA
O
1
FOUTA clock output pin
Outputs a divided OSC3B or OSC1A clock.
FOUTB
O
1
FOUTB clock output pin
Outputs a divided OSC3B or OSC1A clock.
The CLG output pins (FOUTA, FOUTB) are shared with I/O ports and are initially set as general purpose I/O port
pins. The pin functions must be switched using the port function select bits to use the general purpose I/O port pins
as the CLG output pins. For detailed information on pin function switching, see the “I/O Ports (P)” chapter.
Oscillators
7.3
The CLG module contains two internal oscillator circuits (OSC3B and OSC1A). The OSC3B oscillator generates
the main clock for high-speed operation of the S1C17 Core and peripheral circuits. The OSC1A oscillator generates
a sub-clock for timers and low-power operations. The OSC3B clock is selected as the system clock after an initial
reset. Oscillator on/off switching and system clock selection (from OSC3B and OSC1A) are controlled with soft-
ware.
OSC3B Oscillator
7.3.1
The OSC3B oscillator initiates high-speed oscillation without external components. It initiates oscillation when
power is turned on. The S1C17 Core and peripheral circuits operate with this oscillation clock after an initial reset.
f
OSC3B
Clock
generator
Oscillation stabilization
wait circuit
OSC3BEN
OSC3BWT[1:0]
SLEEP/NORMAL
OSC3BFSEL[1:0]
3.1.1 OSC3B Oscillator Circuit
Figure 7.
OSC3B oscillation frequency selection
The OSC3B oscillation frequency can be selected from three types shown below using OSC3BFSEL[1:0]/
CLG_SRC register.
3.1.1 OSC3B Oscillation Frequency Setting
Table 7.
OSC3BFSel[1:0]
OSC3B oscillation frequency (typ.)
0x3
Reserved
0x2
500 kHz
0x1
1 MHz
0x0
2 MHz
(Default: 0x0)
OSC3B oscillation on/off
The OSC3B oscillator stops oscillating when OSC3BEN/CLG_CTL register is set to 0 and starts oscillating
when set to 1. The OSC3B oscillator stops oscillating in SLEEP mode.
After an initial reset, OSC3BEN is set to 1, and the OSC3B oscillator goes on. Since the OSC3B clock is used
as the system clock, the S1C17 Core starts operating using the OSC3B clock.
