14 uaRT
14-6
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
Data reception control
The receiver circuit is activated by setting RXEN to 1, enabling data to be received from an external serial de-
vice.
When the external serial device sends a start bit, the receiver circuit detects its Low level and starts sampling
the following data bits. The data bits are sampled at the sampling clock rising edge, and the lead bit is loaded
into the receive shift register as LSB. Once the MSB has been received into the shift register, the received data
is loaded into the receive data buffer. If parity checking is enabled, the receiver circuit checks the received data
at the same time by checking the parity bit received immediately after the MSB.
The receive data buffer, a 2-byte FIFO, receives data until full.
Received data in the buffer can be read from RXD[7:0]/UART_RXD
x
register. The oldest data is read out first
and data is cleared by reading.
The receiver circuit includes two buffer status flags: RDRY/UART_ST
x
register and RD2B/UART_ST
x
regis-
ter.
The RDRY flag indicates that the receive data buffer still contains data. The RD2B flag indicates that the re-
ceive data buffer is full.
(1) RDRY = 0, RD2B = 0
The receive data buffer contents need not be read, since no data has been received.
(2) RDRY = 1, RD2B = 0
One 8-bit data has been received. Read the receive data buffer contents once. This resets the RDRY flag.
The buffer reverts to state (1) above.
If the receive data buffer contents are read twice, the second data read will be invalid.
(3) RDRY = 1, RD2B = 1
Two 8-bit data have been received. Read the receive data buffer contents twice. The receive data buffer
outputs the oldest data first. This resets the RD2B flag. The buffer then reverts to the state in (2) above. The
second read outputs the most recent received data, after which the buffer reverts to the state in (1) above.
Even when the receive data buffer is full, the shift register can start receiving 8-bit data one more time. An
overrun error will occur if receiving is finished before the receive data buffer has been read. In this case, the
last received data cannot be read. The contents of the receive data buffer must be read out before an overrun
error occurs. For detailed information on overrun errors, refer to Section 14.6.
The volume of data received can be checked by reading these flags.
The UART allows receive buffer full interrupts to be generated once data has been received in the receive data
buffer. These interrupts can be used to read the receive data buffer. By default, a receive buffer full interrupt
occurs when the receive data buffer receives one 8-bit data (status (2) above). This can be changed by setting
RBFI/UART_CTL
x
register to 1 so that an interrupt occurs when the receive data buffer receives two 8-bit data.
Three error flags are also provided in addition to the flags previously mentioned. See Section 14.6 for detailed
information on flags and receive errors.
