6 inTeRRuPT COnTROlleR (iTC)
6-2
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
Vector Table
6.2
The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be
read by the S1C17 Core to execute the handler when an interrupt occurs.
Table 6.2.1 shows the vector table of the S1C17153.
2.1 Vector Table
Table 6.
Vector no.
Software interrupt no.
Vector address
hardware interrupt name
Cause of hardware interrupt
Priority
0 (0x00)
TTBR + 0x00
Reset
• Low input to the #RESET pin
• Watchdog timer overflow
*
2
1
1 (0x01)
TTBR + 0x04
Address misaligned interrupt
Memory access instruction
2
–
(0xfffc00)
Debugging interrupt
brk
instruction, etc.
3
2 (0x02)
TTBR + 0x08
NMI
Watchdog timer overflow
*
2
4
3 (0x03)
TTBR + 0x0c
Reserved for C compiler
–
–
4 (0x04)
TTBR + 0x10
P0 port interrupt
P00–P07 port inputs
High
*
1
5 (0x05)
TTBR + 0x14
reserved
–
↑
6 (0x06)
TTBR + 0x18
7 (0x07)
TTBR + 0x1c
Clock timer interrupt
• 32 Hz timer signal
• 8 Hz timer signal
• 2 Hz timer signal
• 1 Hz timer signal
8 (0x08)
TTBR + 0x20
RTC interrupt
• 32 Hz, 8 Hz, 4 Hz, 1 Hz
• 10 s, 1 m, 10 m, 1 h
• Half-day, one day
9 (0x09)
TTBR + 0x24
reserved
–
10 (0x0a)
TTBR + 0x28
LCD interrupt
Frame signal
11 (0x0b)
TTBR + 0x2c
16-bit PWM timer Ch.0 interrupt
• Compare A/B
• Capture A/B
• Capture A/B overwrite
12 (0x0c)
TTBR + 0x30
reserved
–
13 (0x0d)
TTBR + 0x34
14 (0x0e)
TTBR + 0x38
8-bit timer Ch. 0 interrupt
Timer underflow
15 (0x0f)
TTBR + 0x3c
reserved
–
16 (0x10)
TTBR + 0x40
UART Ch.0 interrupt
• Transmit buffer empty
• End of transmission
• Receive buffer full
• Receive error
17 (0x11)
TTBR + 0x44
reserved
–
18 (0x12)
TTBR + 0x48
SPI Ch.0 interrupt
• Transmit buffer empty
• Receive buffer full
19 (0x13)
TTBR + 0x4c
reserved
–
:
:
:
:
↓
31 (0x1f)
TTBR + 0x7c
reserved
–
Low
*
1
*
1 When the same interrupt level is set
*
2 Either reset or NMI can be selected as the watchdog timer interrupt with software.
Vector numbers 4, 7, 8, 10, 11, 14, 16, and 18 are assigned to the maskable interrupts supported by the S1C17153.
Vector table base address
The S1C17153 allows the base (starting) address of the vector table to be set using the MISC_TTBRL and
MISC_TTBRH registers. “TTBR” described in Table 6.2.1 means the value set to these registers. After an ini-
tial reset, the MISC_TTBRL and MISC_TTBRH registers are set to 0x8000. Therefore, even when the vector
table location is changed, it is necessary that at least the reset vector be written to the above address. Bits 7 to 0
in the MISC_TTBRL register are fixed at 0, so the vector table starting address always begins with a 256-byte
boundary address.
