16 lCD DRiVeR (lCD)
16-2
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
lCD Clock
16.3
Figure 16.3.1 shows the LCD clock supply system.
LFRO output
LCLK
Frame signal
LCDTCLKE
FRMCNT[1:0]
Divider
OSC1A
OSC3B
Divider
(1/1024–1/8192)
Divider
(1/64)
LCDTCLKD[1:0]
LCDTCLKSRC[1:0]
3.1 LCD Clock System
Figure 16.
lCD Operating Clock (lClK)
16.3.1
Clock source selection
Select the clock source from OSC3B and OSC1A using LCDTCLKSRC[1:0]/LCD_TCLK register.
3.1.1 Clock Source Selection
Table 16.
lCDTClKSRC[1:0]
Clock source
0x3, 0x2
Reserved
0x1
OSC1A
0x0
OSC3B
(Default: 0x0)
Clock division ratio selection
When the clock source is OSC1a
No division ratio needs to be selected when OSC1A is selected for the clock source. The OSC1A clock is
used as LCLK after dividing by 64 (typ. 512 Hz).
When the clock source is OSC3B
When OSC3B is selected for the clock source, use LCDTCLKD[1:0]/LCD_TCLK register to select the di-
vision ratio.
3.1.2 Clock Division Ratio Selection
Table 16.
lCDTClKD[1:0]
Division ratio
0x3
1/8192
0x2
1/4096
0x1
1/2048
0x0
1/1024
(Default: 0x0)
Select a division ratio so that it will generate the LCLK frequency nearest 512 Hz.
Clock enable
The LCLK supply is enabled with LCDTCLKE/LCD_TCLK register. The LCDTCLKE default setting is 0,
which stops the clock. Setting LCDTCLKE to 1 feeds the clock generated as above to the LCD driver. If no
LCD display is required, stop the clock to reduce current consumption.
If LCLK is not supplied, the LCD cannot display. However, the LCD driver control registers and display mem-
ory can be accessed even if LCLK is stopped.
note
: Be sure to set LCDTCLKE to 0 before selecting a clock division ratio.
