14 uaRT
S1C17153 TeChniCal Manual
Seiko epson Corporation
14-7
(Rev. 1.0)
Receive buffer full interrupt request
(RBFI = 0)
Overrun error
interrupt request
Sampling clock (sclk)
SIN
x
Receive data buffer
RDRY
RD2B
RXD[7:0]
Interrupt
data 1
S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2
data 2
data 3
data 4
data 5
data 6
Rd
Rd
data 3, 4
data 2
data 1
–
data 2, 3 data 3
data 3
data 2
data 1
S1: Start bit, S2: Stop bit, P: Parity bit, Rd: Data read from RXD[7:0]
5.2 Data Receiving Timing Chart
Figure 14.
Disabling data transfers
Write 0 to RXEN to disable data transfers. The data being transferred cannot be guaranteed if RXEN is set to
0 while data is being sent or received. Before setting RXEN to 0, check the data transfer status with software in
consideration of the communication procedure. The data transmit status can be checked using the TRBS flag.
note
: Setting RXEN to 0 empties the transmit data buffer, clearing any remaining data. The data being
transferred cannot be guaranteed if RXEN is set to 0 while data is being sent or received.
Make sure that the TDBE flag is 1 and the TRBS and RDRY flags are both 0 before disabling data
transfer.
Receive errors
14.6
Three different receive errors may be detected while receiving data.
Since receive errors are interrupt causes, they can be processed by generating interrupts. For more information on
UART interrupt control, see Section 14.7.
Parity error
If PREN/UART_MOD
x
register has been set to 1 (parity enabled), data received is checked for parity.
Data received in the shift register is checked for parity when sent to the receive data buffer. The matching is
checked against the PMD/UART_MOD
x
register setting (odd or even parity). If the result is a non-match, a
parity error is issued, and the parity error flag PER/UART_ST
x
register is set to 1. Even if this error occurs, the
data received is sent to the receive data buffer, and the receiving operation continues. However, the received
data cannot be guaranteed if a parity error occurs. The PER flag is reset to 0 by writing 1.
Framing error
A framing error occurs if the stop bit is received as 0 and the UART determines loss of sync. If the stop bit is
set to two bits, only the first bit is checked.
The framing error flag FER/UART_ST
x
register is set to 1 if this error occurs. The received data is still trans-
ferred to the receive data buffer if this error occurs and the receiving operation continues, but the data cannot be
guaranteed, even if no framing error occurs for subsequent data receiving. The FER flag is reset to 0 by writing 1.
Overrun error
Even if the receive data buffer is full (two 8-bit data already received), the third data can be received in the shift
register. However, if the receive data buffer is not emptied (by reading out data received) by the time this data
has been received, the third data received in the shift register will not be sent to the buffer and generate an over-
run error. If an overrun error occurs, the overrun error flag OER/UART_ST
x
register is set to 1. The receiving
operation continues even if this error occurs. The OER flag is reset to 0 by writing 1.
