15 SPi
S1C17153 TeChniCal Manual
Seiko epson Corporation
15-1
(Rev. 1.0)
SPI
15
SPi Module Overview
15.1
The S1C17153 includes a synchronized serial interface module (SPI).
The following shows the main features of the SPI:
• Number of channels: 1 channel
• Supports both master and slave modes.
• Data length: 8 bits fixed
• Supports both MSB first and LSB first modes.
• Contains one-byte receive data buffer and one-byte transmit data buffer.
• Supports full-duplex communications.
• Data transfer timing (clock phase and polarity variations) is selectable from among 4 types.
• Can generate receive buffer full and transmit buffer empty interrupts.
Figure 15.1.1 shows the SPI module configuration.
Shift register
Receive data
buffer (1 byte)
SDI
x
PCLK
Internal bus
ITC
SPI Ch.
x
Bus I/F
and
control
registers
SPICLK
x
#SPISS
x
Shift register
Transmit data
buffer (1 byte)
Clock/transfer control
SDO
x
T8 Ch.0
output clock
Interrupt
control
1/4
1.1 SPI Module Configuration
Figure 15.
note
: The letter ‘
x
’ in register and pin names refers to a channel number (0).
Example: SPI_CTL
x
register
Ch.0: SPI_CTL0 register
SPi input/Output Pins
15.2
Table 15.2.1 lists the SPI pins.
2.1 List of SPI Pins
Table 15.
Pin name
i/O
Qty
Function
SDI0 (Ch.0)
I
1
SPI data input pin
Inputs serial data from SPI bus.
SDO0 (Ch.0)
O
1
SPI data output pin
Outputs serial data to SPI bus.
SPICLK0 (Ch.0)
I/O
1
SPI external clock input/output pin
Outputs SPI clock when SPI is in master mode.
Inputs external clock when SPI is used in slave mode.
#SPISS0 (Ch.0)
I
1
SPI slave select signal (active Low) input pin
SPI (Slave mode) is selected as a slave device by Low input to this pin.
