aPPenDiX a liST OF i/O ReGiSTeRS
aP-a-6
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
FOuTa Control
Register
(ClG_FOuTa)
0x5064
(8 bits)
D7
–
reserved
–
–
–
0 when being read.
D6–4
FOuTaD
[2:0]
FOUTA clock division ratio select
FOUTAD[2:0]
Division ratio
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
D3–2
FOuTaSRC
[1:0]
FOUTA clock source select
FOUTASRC[1:0] Clock source
0x0 R/W
0x3, 0x2
0x1
0x0
reserved
OSC1A
OSC3B
D1
–
reserved
–
–
–
0 when being read.
D0
FOuTae
FOUTA output enable
1 Enable
0 Disable
0
R/W
FOuTB Control
Register
(ClG_FOuTB)
0x5065
(8 bits)
D7
–
reserved
–
–
–
0 when being read.
D6–4
FOuTBD
[2:0]
FOUTB clock division ratio select
FOUTBD[2:0]
Division ratio
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
D3–2
FOuTBSRC
[1:0]
FOUTB clock source select
FOUTBSRC[1:0] Clock source
0x0 R/W
0x3, 0x2
0x1
0x0
reserved
OSC1A
OSC3B
D1
–
reserved
–
–
–
0 when being read.
D0
FOuTBe
FOUTB output enable
1 Enable
0 Disable
0
R/W
Oscillation
Stabilization
Wait Control
Register
(ClG_WaiT)
0x507d
(8 bits)
D7–6
OSC3BWT
[1:0]
OSC3B stabilization wait cycle
select
OSC3BWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
8 cycles
16 cycles
32 cycles
64 cycles
D5–2
–
reserved
–
–
–
0 when being read.
D1–0
OSC1aWT
[1:0]
OSC1A stabilization wait cycle
select
OSC1AWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
reserved
4096 cycles
reserved
16384 cycles
PClK Control
Register
(ClG_PClK)
0x5080
(8 bits)
D7–2
–
reserved
–
–
–
0 when being read.
D1–0
PCKen[1:0]
PCLK enable
PCKEN[1:0]
PCLK supply
0x3 R/W
0x3
0x2
0x1
0x0
Enable
Not allowed
Not allowed
Disable
CClK Control
Register
(ClG_CClK)
0x5081
(8 bits)
D7–2
–
reserved
–
–
–
0 when being read.
D1–0
CClKGR[1:0]
CCLK clock gear ratio select
CCLKGR[1:0]
Gear ratio
0x0 R/W
0x3
0x2
0x1
0x0
1/8
1/4
1/2
1/1
0x5070–0x5071, 0x50a0–0x50a6
lCD Driver
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
lCD Timing
Clock Select
Register
(lCD_TClK)
0x5070
(8 bits)
D7–6
–
reserved
–
–
–
0 when being read.
D5–4
lCDTClKD
[1:0]
LCD clock division ratio select
LCDTCLKD
[1:0]
Division ratio
0x0 R/W
OSC3B OSC1A
0x3
0x2
0x1
0x0
1/8192
1/4096
1/2048
1/1024
1/64
1/64
1/64
1/64
D3–2
lCDTClK
SRC[1:0]
LCD clock source select
LCDTCLK
SRC[1:0]
Clock source
0x0 R/W
0x3, 0x2
0x1
0x0
reserved
OSC1A
OSC3B
D1
–
reserved
–
–
–
0 when being read.
D0
lCDTClKe
LCD clock enable
1 Enable
0 Disable
0
R/W