13 WaTChDOG TiMeR (WDT)
S1C17153 TeChniCal Manual
Seiko epson Corporation
13-3
(Rev. 1.0)
D4
WDTRST: Watchdog Timer Reset Bit
Resets WDT.
1 (W):
Reset
0 (W):
Ignored
0 (R):
Always 0 when read (default)
note
: To use WDT, it must be reset by writing 1 to this bit within the NMI/reset generation cycle (4
seconds when f
OSC1A
= 32.768 kHz). This resets the up-counter to 0 and starts counting with a
new NMI/reset generation cycle.
D[3:0]
WDTRun[3:0]: Watchdog Timer Run/Stop Control Bits
Controls WDT Run/Stop.
Values other than 0b1010 (R/W): Run
0b1010 (R/W):
Stop (default)
note
: WDT must also be reset to prevent generation of an unnecessary NMI or Reset before start-
ing WDT.
Watchdog Timer Status Register (WDT_ST)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
Watchdog
Timer Status
Register
(WDT_ST)
0x5041
(8 bits)
D7–2
–
reserved
–
–
–
0 when being read.
D1
WDTMD
NMI/Reset mode select
1 Reset
0 NMI
0
R/W
D0
WDTST
NMI status
1 NMI occurred 0 Not occurred
0
R
D[7:2]
Reserved
D1
WDTMD: nMi/Reset Mode Select Bit
Selects NMI or reset generation on counter overflow.
1 (R/W): Reset
0 (R/W): NMI (default)
Setting this bit to 1 outputs a reset signal when the counter overflows. Setting to 0 outputs an NMI sig-
nal.
D0
WDTST: nMi Status Bit
Indicates a counter overflow and NMI occurrence.
1 (R):
NMI occurred (counter overflow)
0 (R):
NMI not occurred (default)
This bit confirms that WDT was the source of the NMI. The WDTST set to 1 is cleared to 0 by resetting
WDT.
This is also set by a counter overflow if reset output is selected, but is cleared by initial reset and cannot
be confirmed.
