5 iniTial ReSeT
S1C17153 TeChniCal Manual
Seiko epson Corporation
5-1
(Rev. 1.0)
Initial Reset
5
initial Reset Sources
5.1
The S1C17153 has three initial reset sources that initialize the internal circuits.
(1) #RESET pin (external initial reset)
(2) Key-entry reset using the P0 ports (P00–P03 pins) (software selectable external initial reset)
(3) Watchdog timer (software selectable internal initial reset)
Figure 5.1.1 shows the configuration of the initial reset circuit.
P0 ports
#RESET
Key-entry reset signal
Reset input signal
Internal reset signal
(to core and peripheral modules)
WDT reset signal
P00
P01
P02
P03
Watchdog
timer
1.1 Configuration of Initial Reset Circuit
Figure 5.
The CPU and peripheral circuits are initialized by the active signal from an initial reset source. When the reset sig-
nal is negated, the CPU starts reset handling. The reset handling reads the reset vector (reset handler start address)
from the beginning of the vector table and starts executing the program (initial routine) beginning with the read ad-
dress.
#ReSeT Pin
5.1.1
By setting the #RESET pin to low level, the S1C17153 enters initial reset state. In order to initialize the S1C17153
for sure, the #RESET pin must be held at low for more than the prescribed time (see “Input/Output Pin Characteris-
tics” in the “Electrical Characteristics” chapter) after the power supply voltage is supplied.
When the #RESET pin at low level is set to high level, the CPU starts executing the initial reset sequence.
The #RESET pin is equipped with a pull-up resistor.
P0 Port Key-entry Reset
5.1.2
Entering low level simultaneously to the ports (P00–P03) selected with software triggers an initial reset. For details
of the key-entry reset function, see the “I/O Ports (P)” chapter.
note
: The P0 port key-entry reset function cannot be used for power-on reset as it must be enabled with
software.
Resetting by the Watchdog Timer
5.1.3
The S1C17153 has a built-in watchdog timer to detect runaway of the CPU. The watchdog timer overflows if it is
not reset with software (due to CPU runaway) in four-second cycles. The overflow signal can generate either NMI
or reset. Write 1 to the WDTMD/WDT_ST register to generate reset (NMI occurs when WDTMD = 0).
For details of the watchdog timer, see the “Watchdog Timer (WDT)” chapter.
notes
: • When using the reset function of the watchdog timer, program the watchdog timer so that it
will be reset within four-second cycles to avoid occurrence of an unnecessary reset.
• The reset function of the watchdog timer cannot be used for power-on reset as it must be en-
abled with software.
