11 16-BiT PWM TiMeR (T16a2)
11-4
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
Comparator Mode and Capture Mode
11.4.1
The T16A_CCA
x
and T16A_CCB
x
registers that are embedded in the comparator/capture block can be set to com-
parator mode or capture mode, individually. The T16A_CCA
x
register mode is selected using CCAMD/T16A_
CCCTL
x
register and the T16A_CCB
x
register mode is selected using CCBMD/T16A_CCCTL
x
register.
Comparator mode (CCaMD/CCBMD = 0, default)
The comparator mode compares the counter value and the comparison value set via software. It generates an
interrupt and toggles the timer output signal level when the values are matched. The T16A_CCA
x
and T16A_
CCB
x
registers function as the compare A and compare B registers that are used for loading compare values in
this mode.
When the counter reaches the value set in the compare A register during counting, the comparator asserts the
compare A signal. At the same time the compare A interrupt flag is set and the interrupt signal of the timer
channel is output to the ITC if the interrupt has been enabled.
When the counter reaches the value set in the compare B register, the comparator asserts the compare B signal.
At the same time the compare B interrupt flag is set and the interrupt signal of the timer channel is output to the
ITC if the interrupt is enabled. Furthermore, the counter is reset to 0.
The compare A period (time from start of counting to occurrence of a compare A interrupt) and the compare B
period (time from start of counting to occurrence of a compare B interrupt) can be calculated as follows:
Compare A period = (CCA + 1) / ct_clk [second]
Compare B period = (CCB + 1) / ct_clk [second]
CCA: Compare A register value set (0 to 65535)
CCB: Compare B register value set (0 to 65535)
ct_clk: Count clock frequency [Hz]
The compare A and compare B signals are also used to generate a timer output waveform (TOUT). See Section
11.6, “Timer Output Control,” for more information.
To generate PWM waveform, the T16A_CCA
x
and T16A_CCB
x
registers must be both placed into comparator
mode.
Compare buffers
The compare buffer is used to synchronize the comparison data update timings and the counter operation.
Setting CBUFEN/T16A_CTL
x
register to 1 enables the compare buffer. The compare A and B signals will
be generated by comparing the counter values with the compare A and B buffer values instead of the com-
pare A and B register values. The compare A and B register values written via software are loaded to the
compare A and B buffers when the compare B signal is generated.
note
: When writing data to the T16A_CCA
x
or T16A_CCB
x
register successively, data should be writ-
ten at intervals of one or more T16A2 count clock cycles.
Capture mode (CCaMD/CCBMD = 1)
The capture mode captures the counter value when an external event such as a key entry occurs (at the specified
edge of the external input signal). In this mode, the T16A_CCA
x
and/or T16A_CCB
x
registers function as the
capture A and/or capture B registers.
The table below lists the input pins of the external trigger signals used for capturing counter values. The pin
function of the corresponding ports must be switched for trigger input in advance. See the “I/O Ports (P)” chap-
ter for switching the pin function.
4.1.1 List of Counter Capture Trigger Signal Input Pins
Table 11.
Channel
Trigger input pins
Capture a
Capture B
T16A2 Ch.0
CAPA0
CAPB0
The trigger edge of the signal can be selected using the CAPATRG[1:0]/T16A_CCCTL
x
register for capture A
and CAPBTRG[1:0]/T16A_CCCTL
x
register for capture B.
