9 i/O PORTS (P)
S1C17153 TeChniCal Manual
Seiko epson Corporation
9-5
(Rev. 1.0)
P0 Port Key-entry Reset
9.7
Entering low level simultaneously to the ports (P00–P03) selected with software triggers an initial reset. The ports
used for the reset function can be selected with the P0KRST[1:0]/P0_KRST register.
7.1 Configuration of P0 Port Key-Entry Reset
Table 9.
P0KRST[1:0]
Port used for resetting
0x3
P00, P01, P02, P03
0x2
P00, P01, P02
0x1
P00, P01
0x0
Not used
(Default: 0x0)
For example, if P0KRST[1:0] is set to 0x3, an initial reset will take place when the four ports P00–P03 are set to
low level at the same time.
notes
: • The P0 port key-entry reset function cannot be used for power-on reset as it must be enabled
with software.
• When using the P0 port key-entry reset function, make sure that the designated input ports
will not be simultaneously set to low level while the application program is running.
Control Register Details
9.8
8.1 List of I/O Port Control Registers
Table 9.
address
Register name
Function
0x5200
P0_IN
P0 Port Input Data Register
P0 port input data
0x5201
P0_OUT
P0 Port Output Data Register
P0 port output data
0x5202
P0_OEN
P0 Port Output Enable Register
Enables P0 port outputs.
0x5203
P0_PU
P0 Port Pull-up Control Register
Controls the P0 port pull-up resistor.
0x5205
P0_IMSK
P0 Port Interrupt Mask Register
Enables P0 port interrupts.
0x5206
P0_EDGE
P0 Port Interrupt Edge Select Register
Selects the signal edge for generating P0 port interrupts.
0x5207
P0_IFLG
P0 Port Interrupt Flag Register
Indicates/resets the P0 port interrupt occurrence status.
0x5208
P0_CHAT
P0 Port Chattering Filter Control Register
Controls the P0 port chattering filter.
0x5209
P0_KRST
P0 Port Key-Entry Reset Configuration Register Configures the P0 port key-entry reset function.
0x520a
P0_IEN
P0 Port Input Enable Register
Enables P0 port inputs.
0x5210
P1_IN
P1 Port Input Data Register
P1 port input data
0x5211
P1_OUT
P1 Port Output Data Register
P1 port output data
0x5212
P1_OEN
P1 Port Output Enable Register
Enables P1 port outputs.
0x5213
P1_PU
P1 Port Pull-up Control Register
Controls the P1 port pull-up resistor.
0x521a
P1_IEN
P1 Port Input Enable Register
Enables P1 port inputs.
0x52a0
P00_03PMUX P0[3:0] Port Function Select Register
Selects the P0[3:0] port functions.
0x52a1
P04_07PMUX P0[7:4] Port Function Select Register
Selects the P0[7:4] port functions.
0x52a2
P10_13PMUX P1[3:0] Port Function Select Register
Selects the P1[3:0] port functions.
The I/O port registers are described in detail below.
note
: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
P
x
Port input Data Registers (P
x
_in)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
P
x
Port input
Data Register
(P
x
_in)
0x5200
0x5210
(8 bits)
D7–0
P
x
in[7:0]
P
x
[7:0] port input data
1 1 (H)
0 0 (L)
×
R
note
: P1IN[3:0] only are available for the P1 ports. Other bits are reserved and always read as 0.
D[7:0]
P
x
in[7:0]: P
x
[7:0] Port input Data Bits
The port pin status can be read out. (Default: external input status)
1 (R):
High level
0 (R):
Low level
