11 16-BiT PWM TiMeR (T16a2)
S1C17153 TeChniCal Manual
Seiko epson Corporation
11-1
(Rev. 1.0)
16-bit PWM Timer (T16A2)
11
T16a2 Module Overview
11.1
The S1C17153 includes a 16-bit PWM timer (T16A2) module that consists of counter blocks and comparator/
capture blocks. This timer can be used as an interval timer, PWM waveform generator, external event counter and a
count capture unit to measure external event periods.
The features of T16A2 are listed below.
• One channel of 16-bit up counter block
• One channel of comparator/capture block
• Allows selection of a count clock asynchronously with the CPU clock.
• Supports event counter function using an external clock.
• The comparator compares the counter value with two specified comparison values to generate interrupts and a
PWM waveform.
• The capture unit captures counter values using two external trigger signals and generates interrupts.
Figure 11.1.1 shows the T16A2 configuration.
Capture
circuit
Comparator
circuit
Compare B
buffer
Compare A
buffer
Comparator
circuit
TOUT
control circuit
Interrupt
control circuit
TOUTA0
TOUTB0
CAPA0
CAPB0
Interrupt request
Compare B/Capture B register
T16A_CCB0
Compare A/Capture A register
T16A_CCA0
Counter block Ch.0
Comparator/capture block Ch.0
Counter
T16A_TC0
0
1
3
Divider
(1/1–1/16384)
Divider
(1/1–1/256)
OSC3B
EXCL0
T16ACLKD[3:0]
/T16A_CLK0
T16ACLKE
/T16A_CLK0
T16ACLKSRC[1:0]
/T16A_CLK0
OSC1A
HCM, TRMD,
PRESET, PRUN
/T16A_CTL0
Compare A
signal
Compare B
signal
Gate
Clock controller Ch.0
16-bit PWM timer (T16A2)
CBUFEN
/T16A_CTL0
CBUFEN
/T16A_CTL0
T16A_IFLG0
T16A_CCCTL0
T16A_IEN0
1
0
1
0
1.1 T16A2 Configuration
Figure 11.
Clock controller
T16A2 includes a clock controller that generates the count clock for the counter. The clock source and division
ratio can be selected with software.
Counter block
The counter block includes a 16-bit up-counter that operates with an OSC3B or OSC1A division clock, or the
external count clock input from outside the IC. The T16A2 module allows software to run and stop the counter,
and to reset the counter value (cleared to 0) as well as selection of the count clock. The counter can also be reset
by the compare B signal output from the comparator/capture block.
