12 ClOCK TiMeR (CT)
S1C17153 TeChniCal Manual
Seiko epson Corporation
12-1
(Rev. 1.0)
Clock Timer (CT)
12
CT Module Overview
12.1
The S1C17153 includes a clock timer module (CT) that uses the OSC1A oscillator as its clock source. This timer
can be used for generating cyclic interrupts to implement a software clock function.
The features of the CT module are listed below.
• 8-bit binary counter (128 Hz to 1 Hz)
• 32 Hz, 8 Hz, 2 Hz, and 1 Hz interrupts can be generated.
Figure 12.1.1 shows the CT configuration.
Internal data bus
Clock timer interrupt request
To ITC
128
Hz
64
Hz
32
Hz
16
Hz
8
Hz
4
Hz
2
Hz
1
Hz
Count
control circuit
Interrupt
control circuit
Run/Stop control
Interrupt
enable
CTRUN
CTIE32
CTIE8
CTIE2
CTIE1
Timer reset
CTRST
CT_CNT
D0
D1
D2
D3
D4
D5
D6
D7
Clock timer
RTC reset
SLEEP/NORMAL
32 kHz
256 Hz
OSC1A
oscillator
OSC1A
divider
CLG
1.1 CT Configuration
Figure 12.
The CT module consists of an 8-bit binary counter that uses the 256 Hz signal divided from the OSC1A clock as
the input clock and allows data for each bit (128 Hz to 1 Hz) to be read out by software. The clock timer can also
generate interrupts using the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals. This clock timer is normally used for various
timing functions, such as a clock.
Operation Clock
12.2
The CT module uses the 256 Hz clock output by the CLG module (256 Hz clock derived from the OSC1A divider)
the operation clock. Therefore, the OSC1A oscillator must be turned on before starting the CT module. However,
the clock is not supplied to the CT module in SLEEP mode even if the OSC1A oscillator is on. For detailed infor-
mation on clock control, see the “Clock Generator (CLG)” chapter.
notes
: • The CT module input clock frequency is 256 Hz only when the OSC1A clock frequency is
32.768 kHz. The frequency described in this chapter will vary accordingly for other OSC1A
clock frequencies.
• The OSC1A divider is reset when the RTC starts running (when 1 is written to RTCRUN/RTC_
CTL register). This affects the count operations of the CT module, as new 256 Hz clock cycle
begins from that point.
Timer Reset
12.3
Reset the timer by writing 1 to CTRST/CT_CTL register. This clears the counter to 0.
Apart from this operation, the counter is also cleared by an initial reset.
