5 iniTial ReSeT
5-2
Seiko epson Corporation
S1C17153 TeChniCal Manual
(Rev. 1.0)
initial Reset Sequence
5.2
Even if the #RESET pin input negates the reset signal after power is turned on, the CPU cannot boot up until the
oscillation stabilization waiting time (64/OSC3B clock frequency) and the internal reset hold period (32/OSC3B
clock frequency) have elapsed.
Figure 5.2.1 shows the operating sequence following cancellation of initial reset.
The CPU starts operating in synchronization with the OSC3B (internal oscillator) clock after reset state is canceled.
note
: The oscillation stabilization time described in this section does not include oscillation start time.
Therefore the time interval until the CPU starts executing instructions after power is turned on or
SLEEP mode is canceled may be longer than that indicated in the figure below.
Boot vector
OSC3B oscillation
stabilization waiting
time
Internal reset
hold period
Booting
OSC3B clock
#RESET
Internal reset
Internal data request
Internal data address
Internal reset canceled
Reset canceled
2.1 Operation Sequence Following Cancellation of Initial Reset
Figure 5.
initial Settings after an initial Reset
5.3
The CPU internal registers are initialized as follows at initial reset.
R0–R7: 0x0
PSR:
0x0 (interrupt level = 0, interrupt disabled)
SP:
0x0
PC:
Reset vector stored at the beginning of the vector table is loaded by the reset handling.
The internal RAM should be initialized with software as it is not initialized at initial reset.
The internal peripheral modules are initialized to the default values (except some undefined registers). Change the
settings with software if necessary. For the default values set at initial reset, see the list of I/O registers in Appendix
or descriptions for each peripheral module.
