7 ClOCK GeneRaTOR (ClG)
S1C17153 TeChniCal Manual
Seiko epson Corporation
7-1
(Rev. 1.0)
Clock Generator (CLG)
7
ClG Module Overview
7.1
The clock generator (CLG) controls the internal oscillators and the system clocks to be supplied to the S1C17 Core,
on-chip peripheral modules, and external devices.
The features of the CLG module are listed below.
• Generates the operating clocks with the built-in oscillators.
- OSC3B oscillator circuit: 2 MHz/1 MHz/500 kHz (typ.) internal oscillator circuit
- OSC1A oscillator circuit: 32.768 kHz (typ.) crystal oscillator circuit
• Switches the system clock. The system clock source can be selected from OSC3B and OSC1A via software.
• Generates the CPU core clock (CCLK) and controls the clock supply to the core block. The CCLK frequency can
be selected from system clock
×
1/1, 1/2, 1/4, and 1/8.
• Controls the clock supply to the peripheral modules.
• Turns the clocks on and off according to the CPU operating status (RUN, HALT, or SLEEP).
• Supports quick-restart processing from SLEEP mode.
Turns OSC3B on forcibly and switches the system clock to OSC3B when SLEEP mode is canceled.
• Controls two clock outputs to external devices.
Figure 7.1.1 shows the clock system and CLG module configuration.
CCLK
FOUTA
output circuit
OSC3B
oscillator
(0.5/1/2 MHz)
Clock gear
(1/1–1/8)
OSC
controller
Gate
S1C17 Core
System
clock
RTC reset
OSC1A
dividing
signals
OSC3B
OSC1A
FOUTA
FOUTB
output circuit
FOUTB
OSC1A
oscillator
(32.768 kHz)
OSC1
OSC2
SLEEP, wakeup
CLG
T8, ITC, SPI, P,
MISC, VD1
PCLK
T16A2
Gate
LCD, UART, SND
OSC3B
divider
256 Hz
RTC
CT, WDT
HALT
Gate
SLEEP
OSC1A
divider
1.1 CLG Module Configuration
Figure 7.
To reduce current consumption, control the clock in conjunction with processing and use HALT and SLEEP modes.
For more information on reducing current consumption, see “Power Saving” in the appendix chapter.
