aPPenDiX C MOunTinG PReCauTiOnS
S1C17153 TeChniCal Manual
Seiko epson Corporation
aP-C-1
(Rev. 1.0)
Appendix C Mounting Precautions
This section describes various precautions for circuit board design and IC mounting.
Oscillator circuit
• Oscillation characteristics depend on factors such as components used (resonator, C
G
, C
D
) and circuit board
patterns. In particular, with ceramic or crystal resonators, select the appropriate capacitors (C
G
, C
D
) only af-
ter fully evaluating components actually mounted on the circuit board.
• Oscillator clock disturbances caused by noise may cause malfunctions. To prevent such disturbances, consid-
er the following points. The latest devices, in particular, are manufactured by microscopic processes, making
them especially susceptible to noise.
Areas in which noise countermeasures are especially important include the OSC2 pin and related circuit
components and wiring. OSC1 pin handling is equally important. The noise precautions required for the
OSC1 and OSC2 pins are described below.
(1) Components such as a resonator, resistors, and capacitors connected to the OSC1 and OSC2 pins should
have the shortest connections possible.
(2) Wherever possible, avoid locating digital signal lines within 3 mm of the OSC1 and OSC2 pins or related
circuit components and wiring. Rapidly-switching signals, in particular, should be kept at a distance from
these components. Since the spacing between layers of multi-layer printed circuit boards is a mere 0.1 mm
to 0.2 mm, the above precautions also apply when positioning digital signal lines on other layers.
Never place digital signal lines alongside such components or wiring, even if more than 3 mm distance or
located on other layers. Avoid crossing wires.
(3) Use V
SS
to shield OSC1 and OSC2 pins and related wiring (including wiring for adjacent circuit board lay-
ers). Layers wired should be adequately shielded as much as possible. Fully ground adjacent layers, where
possible. At minimum, shield the area at least 5 mm around the above pins and wiring.
Even after implementing these precautions, avoid configuring digital signal lines in parallel, as described in
(2) above. Avoid crossing even on discrete layers, except for lines carrying signals with low switching fre-
quencies.
(4) After implementing these precautions, check the output clock waveform by running the actual application
program within the product.
You can check the quality of the OSC1A waveform via the FOUTA or FOUTB output. In particular, enlarge
the areas before and after the clock rising and falling edges and take special care to confirm that the regions
approximately 100 ns to either side are free of clock or spiking noise.
Failure to observe precautions (1) to (3) adequately may lead to noise in the OSC1A output. Noise in the
OSC1A output will destabilize timers operated by the OSC1A clock as well as CPU Core operations when
the system clock switches to OSC1A.
Reset circuit
• The reset signal input to the #RESET pin when power is turned on will vary, depending on various factors,
such as power supply start-up time, components used, and circuit board patterns. Constants such as capaci-
tance and resistance should be determined through testing with real-world products.
• Components such as capacitors and resistors connected to the #RESET pin should have the shortest connec-
tions possible to prevent noise-induced resets.
Power supply circuit
Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues.
(1) Connections from the power supply to the V
DD
and V
SS
pins should be implemented via the shortest, thick-
est patterns possible.
(2) If a bypass capacitor is connected between V
DD
and V
SS
, connections between the V
DD
and V
SS
pins should
be as short as possible.
