Seiko Epson S1C17153, Technical Manual

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14 uaRT
S1C17153 TeChniCal Manual
Seiko epson Corporation 14-15
(Rev. 1.0)
uaRT Ch. x Fine Mode Register (uaRT_FMD x )
Register name address Bit name Function Setting init. R/W Remarks
uaRT Ch. x
Fine Mode
Register
(uaRT_FMD
x )
0x4107
(8 bits)
D7–4
–
reserved – – – 0 when being read.
D3–0 FMD[3:0] Fine mode setup 0x0 to 0xf 0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
D[7:4] Reserved
D[3:0] FMD[3:0]: Fine Mode Setup Bits
Corrects the transfer rate error. (Default: 0x0)
FMD[3:0] specifies the delay pattern to be inserted into a 16 underflow period of the baud rate genera-
tor output clock. Inserting one delay extends the output clock cycle by one count clock cycle.
9.2 Delay Patterns Specified by FMD[3:0] Table 14.
FMD[3:0]
underflow number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0x0 – – – – – – – – – – – – – – – –
0x1 – – – – – – – – – – – – – – – D
0x2 – – – – – – – D – – – – – – – D
0x3 – – – – – – – D – – – D – – – D
0x4 – – – D – – – D – – – D – – – D
0x5 – – – D – – – D – – – D – D – D
0x6 – – – D – D – D – – – D – D – D
0x7 – – – D – D – D – D – D – D – D
0x8 – D – D – D – D – D – D – D – D
0x9 – D – D – D – D – D – D – D D D
0xa – D – D – D D D – D – D – D D D
0xb – D – D – D D D – D D D – D D D
0xc – D D D – D D D – D D D – D D D
0xd – D D D – D D D – D D D D D D D
0xe – D D D D D D D – D D D D D D D
0xf – D D D D D D D D D D D D D D D
D: Indicates the insertion of a delay cycle.
Count clock
Underflow signal (not corrected)
Underflow signal (corrected)
sclk (not corrected)
sclk (corrected)
Delayed
15 16
15 16
1
1
9.1 Delay Cycle Insertion in Fine Mode Figure 14.
uaRT Ch. x Clock Control Register (uaRT_ClK x )
Register name address Bit name Function Setting init. R/W Remarks
uaRT Ch. x
Clock Control
Register
(uaRT_ClK
x )
0x506c
(8 bits)
D7–6
–
reserved – – – 0 when being read.
D5–4
uTClKD
[1:0]
Clock division ratio select UTCLKD[1:0] Division ratio 0x0 R/W When the clock
source is OSC3B 0x3
0x2
0x1
0x0 1/8
1/4
1/2
1/1
D3–2 uTClKSRC
[1:0] Clock source select UTCLKSRC
[1:0]
Clock source
0x0 R/W
0x3
0x2
0x1
0x0 External clock
reserved
OSC1A
OSC3B
D1 – reserved – – – 0 when being read.
D0
uTClKe
Count clock enable 1 Enable 0 Disable 0 R/W
D[7:6] Reserved