6 inTeRRuPT COnTROlleR (iTC)
S1C17153 TeChniCal Manual
Seiko epson Corporation
6-5
(Rev. 1.0)
halT and SleeP Mode Cancellation
6.6
HALT and SLEEP modes are cleared by the following signals, which start the CPU.
• Interrupt request signal sent to the CPU from the ITC
• NMI signal output by the watchdog timer
• Reset signal
notes
: • If the CPU is able to receive interrupts when HALT or SLEEP mode has been cleared by an
interrupt request for the CPU from the ITC, processing branches to the interrupt handler rou-
tine immediately after cancellation. In all other cases, the program is executed following the
halt
or
slp
instruction.
• HALT or SLEEP mode clearing due to interrupt requests cannot be masked (prohibited) using
ITC interrupt level settings.
For more information, see “Power Saving by Clock Control” in the appendix chapter. For the oscillator circuit and
system clock statuses after HALT or SLEEP mode is canceled, see the “Clock Generator (CLG)” chapter.
Control Register Details
6.7
7.1 List of ITC Registers
Table 6.
address
Register name
Function
0x4306
ITC_LV0
Interrupt Level Setup Register 0
Sets the P0 interrupt level.
0x4308
ITC_LV1
Interrupt Level Setup Register 1
Sets the CT interrupt level.
0x430a
ITC_LV2
Interrupt Level Setup Register 2
Sets the RTC interrupt level.
0x430c
ITC_LV3
Interrupt Level Setup Register 3
Sets the LCD and T16A2 Ch.0 interrupt levels.
0x4310
ITC_LV5
Interrupt Level Setup Register 5
Sets the T8 Ch.0 interrupt level.
0x4312
ITC_LV6
Interrupt Level Setup Register 6
Sets the UART Ch.0 interrupt level.
0x4314
ITC_LV7
Interrupt Level Setup Register 7
Sets the SPI Ch.0 interrupt level.
note
: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
interrupt level Setup Register
x
(iTC_lV
x
)
Register name address
Bit
name
Function
Setting
init. R/W
Remarks
interrupt level
Setup Register
x
(iTC_lV
x
)
0x4306
|
0x4314
(16 bits)
D15–11
–
reserved
–
–
–
0 when being read.
D10–8
ilV
n
[2:0]
INTn
(1, 3, ... 7) interrupt level
0 to 7
0x0 R/W
D7–3
–
reserved
–
–
–
0 when being read.
D2–0
ilV
n
[2:0]
INTn
(0, 2, ... 14) interrupt level
0 to 7
0x0 R/W
D[15:11], D[7:3]
Reserved
D[10:8], D[2:0]
ilV
n
[2:0]:
INTn
interrupt level Bits (
n
= 0–14)
Sets the interrupt level (0 to 7) of each interrupt. (Default: 0x0)
The S1C17 Core does not accept interrupts with a level set lower than the PSR IL value.
The ITC uses the interrupt level when multiple interrupt requests occur simultaneously.
If multiple interrupt requests enabled by the interrupt enable bit occur simultaneously, the ITC sends the
interrupt request with the highest level set by the ITC_LV
x
registers (0x4306 to 0x4314) to the S1C17
Core.
If multiple interrupt requests with the same interrupt level occur simultaneously, the interrupt with the
lowest vector number is processed first.
The other interrupts are held until all interrupts of higher priority have been accepted by the S1C17
Core.
