CHAPTER 7 DMAC
Preliminary User’s Manual A14874EJ3V0UM
173
(2) Flyby transfer
Similar to the 2-cycle transfer, the next DMARQn signal is acknowledged when its sampling is started at the rise
of VBCLK three clocks following the completion of the write cycle of the current 2-cycle transfer. Actually, when
the specified DMARQn setup time is satisfied after VBCLK falls 2.5 clocks after completion of the write cycle, the
next DMARQn signal request is acknowledged. Therefore, in order to transfer only once, it is recommended that
the DMARQn signal be made inactive within 2 clocks of the end of the write cycle of a 2-cycle single transfer (n =
3 to 0).
7.9 Transfer Types
7.9.1 Two-cycle transfer
In a 2-cycle transfer, data is transferred in 2 cycles: a read cycle (transfer source to DMAC) and a write cycle
(DMAC to transfer destination).
In the first cycle, the transfer source address is output to read data from the transfer source to the DMAC. In the
second cycle, the transfer destination address is output to write data from the DMAC to the transfer destination.
The signals indicating 2-cycle DMA transfer (1, 1, 0) are output from the VMCTYP2 to VMCTYP0 pins.
Caution A one-clock idle cycle is always inserted between a read cycle and a write cycle.
Figure 7-24. Example of Two-Cycle Transfer
Memory
(transfer source)
A
CE
OE
D
Memory
(transfer destination)
A
CE
D
WE
VBDI31 to VBDI0
NU85E
VDCSZn
VBDO31 to VBDO0
VMA25 to VMA0
VMCTYP2 to VMCTYP0
A25 to A0
CSZn
DI31 to DI0
RDZ
NT85E500
CSZn
WRZ
VBDO31 to VBDO0
VBDI31 to VBDI0
VDCSZn
VBA25 to VBA0
VBCTYP2 to VBCTYP0
DO31 to DO0
Remark
n = 7 to 0
