Preliminary User’s Manual A14874EJ3V0UM
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CHAPTER 4 BCU
The bus control unit (BCU), which operates as a bus master on the VSB, controls the on-chip bus bridge (BBR),
test interface control unit (TIC), and peripheral macros (bus slaves) such as the external memory controller (MEMC)
connected to the VSB.
4.1 Features
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32-bit independent I/O separated data bus
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One bus clock transfer between consecutive clock falling edges
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Data transfer in 8-bit, 16-bit, or 32-bit units on a 32-bit bus by means of the bus size function
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Bus arbitration for a multi-master system
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Programmable chip select function
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Programmable peripheral I/O area select function
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Endian setting function
4.2 Memory Banks
The data area is subdivided into multiple units called banks.
The BCU makes bus size, endian, and cache settings in terms of units called “CSn area”, which are arbitrary
combinations of banks.
“CSn area” settings are made based on the VDCSZn signals corresponding to each bank (n = 7 to 0).
