Preliminary User’s Manual A14874EJ3V0UM
13
LIST OF FIGURES (1/3)
Figure No. Title Page
2-1
Acknowledgement of DCRESZ Signal............................................................................................................... 34
2-2
Stopping VBCLK Oscillation by System Reset .................................................................................................. 35
3-1
List of CPU Registers ........................................................................................................................................ 52
3-2
Program Counter (PC)....................................................................................................................................... 54
3-3
Interrupt Source Register (ECR) ....................................................................................................................... 56
3-4
Program Status Word (PSW)............................................................................................................................. 57
3-5
Address Space .................................................................................................................................................. 58
3-6
Program Area .................................................................................................................................................... 59
3-7
Data Area (64 MB Mode)................................................................................................................................... 60
3-8
Data Area (256 MB Mode)................................................................................................................................. 61
3-9
ROM Area.......................................................................................................................................................... 62
3-10
RAM Area .......................................................................................................................................................... 64
3-11
Peripheral I/O Area............................................................................................................................................ 66
3-12
Connection of NU85E and N-Wire Type In-Circuit Emulator via RCU............................................................... 73
4-1
Chip Area Select Control Register 0 (CSC0)..................................................................................................... 77
4-2
Chip Area Select Control Register 1 (CSC1)..................................................................................................... 78
4-3
CSC0 and CSC1 Register Setting Example (64 MB Mode) .............................................................................. 79
4-4
CSC0 and CSC1 Register Setting Example (256 MB Mode) ............................................................................ 82
4-5
Peripheral I/O Area and Programmable Peripheral I/O Area............................................................................. 84
4-6
Peripheral I/O Area Select Control Register (BPC) ........................................................................................... 85
4-7
Bus Size Configuration Register (BSC) ............................................................................................................. 86
4-8
Endian Configuration Register (BEC) ................................................................................................................ 87
4-9
Word Data Little Endian Format Example ......................................................................................................... 88
4-10
Word Data Big Endian Format Example............................................................................................................ 88
4-11
Cache Configuration Register (BHC) ................................................................................................................ 90
4-12
BPC, BSC, BEC, BHC Register Setting Example ............................................................................................. 91
4-13
Example of Data Transfer Using VSB ............................................................................................................... 94
4-14
Read/Write Timing of Bus Slave Connected to VSB ......................................................................................... 99
4-15
VSB Timing Example....................................................................................................................................... 111
4-16
Reset Timing ................................................................................................................................................... 113
4-17
Bus Master Transition Timing.......................................................................................................................... 115
4-18
Misalign Access Timing ................................................................................................................................... 116
5-1
NPB Connection Overview .............................................................................................................................. 118
5-2
NU85E and Peripheral Macro Connection Example........................................................................................ 119
5-3
Peripheral I/O Area and Programmable Peripheral I/O Area........................................................................... 120
5-4
Peripheral I/O Area Select Control Register (BPC) ......................................................................................... 121
5-5
BPC Register Setting Example........................................................................................................................ 122
5-6
NPB Strobe Wait Control Register (VSWC) .................................................................................................... 123
5-7
Retry Function ................................................................................................................................................. 125
5-8
Halfword Access Timing .................................................................................................................................. 126
5-9
Timing of Byte Access to Odd Address ........................................................................................................... 127
5-10
Timing of Byte Access to Even Address.......................................................................................................... 127
